• Title/Summary/Keyword: on-chip

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High Electrical Current Stressing Effects on the Failure Mechanisms of Austudbumps/ACFFlip Chip Joints (고전류 스트레싱이 금스터드 범프를 이용한 ACF 플립칩 파괴 기구에 미치는 영향)

  • Kim Hyeong Jun;Gwon Un Seong;Baek Gyeong Uk
    • Proceedings of the International Microelectronics And Packaging Society Conference
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    • 2003.11a
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    • pp.195-202
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    • 2003
  • In this study, failure mechanisms of Au stud bumps/ACF flip chip joints were investigated underhigh current stressing condition. For the determination of allowable currents, I-V tests were performed on flip chip joints, and applied currents were measured as high as almost 4.2Amps $(4.42\times10^4\;Amp/cm^2)$. Degradation of flip chip joints was observed by in-situ monitoring of Au stud bumps-Al pads contact resistance. All failures, defined at infinite resistance, occurred at upward electron flow (from PCB pads to chip pads) applied bumps (UEB). However, failure did not occur at downward electron flow applied bumps (DEB). Only several $m\Omega$ contact resistance increased because of Au-Al intermetallic compound (IMC) growth. This polarity effect of Au stud bumps was different from that of solder bumps, and the mechanism was investigated by the calculation of chemical and electrical atomic flux. According to SEM and EDS results, major IMC phase was $Au_5Al_2$, and crack propagated along the interface between Au stud bump and IMC resulting in electrical failures at UEB. Therefore. failure mechanisms at Au stud bump/ACF flip chip Joint undo high current density condition are: 1) crack propagation, accompanied with Au-Al IMC growth. reduces contact area resulting in contact resistance increase; and 2) the polarity effect, depending on the direction of electrons. induces and accelerates the interfacial failure at UEBs.

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Microfabricated Cell Chip for Cell-based in vitro Assay

  • Park, Je-Gyun;Kim, Tae-Han;Lee, Sang-Eun;Kim, Su-Hyeon;Yun, Gyu-Sik;Lee, Jeong-Geon
    • 한국생물공학회:학술대회논문집
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    • 2000.11a
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    • pp.115-118
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    • 2000
  • A microfabricated cell chip was developed to evaluate drug effect on mouse B16-F1 melanoma cell line. The cell chip system consists of 8-well culture cartridge incorporated with interdigitated array gold electrodes on each well, lock-in amplifier, 8-well cell scanner and computer as a system controller. Impedance of an electrode is increased according to adherent cell growth on the electrode surface. In order to verify investigated. The change of impedance was measured differentially between a control electrode containing only media and cell-cultured sample electrodes with time.

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An Analysis of the ESD Protection Characteristic of Chip Varistors Using a Distributed Circuit (분산회로를 이용한 칩 바리스터의 ESD 보호 특성에 대한 분석)

  • Hong Sung-Mo;Lee Jong-Geun;Chung Duck-Jin;Kim Ju-Min
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.53 no.12
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    • pp.589-595
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    • 2004
  • The ESD protection characteristic of chip varistors on a circuit board can not be analyzed by using a conventional circuit simulator due to its microwave characteristic. Thus, by employing Agilent's microwave circuit simulator ADS, we showed that the ESD Protection characteristic or chip varistors can be investigated. order to got more precise simulation results, a chip varistor model was extracted from the electrical characteristic of a TDK's chip varistor and the distributed circuit based pattern was designed as the ESD propagation path. The simulation results showed that the ESD protection characteristic of a chip varistors can be improved drastically by reducing the ESD propagation path.

Design of a New ISFET Array Chip

  • Yeow, Terence;Seo, Hwa-Il;Mulcahy, Dennis;Haskard, Malcolm
    • Journal of Sensor Science and Technology
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    • v.4 no.4
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    • pp.55-61
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    • 1995
  • A new ISFET array chip, based on detection of the threshold voltages of ISFETs by using an adjustable input, was designed. The chip includes 240 pH-ISFETs and circuitry such as comparators, a decoder and register. The chip has increased reliability, improved accuracy, digital output capability and the possibility of multi sensor implementation. To fabricate the chip, an extended CMOS process was devised and implemented.

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Fabrication of a CNT Filter for a Microdialysis Chip

  • An, Yun-Ho;Song, Si-Mon
    • Molecular & Cellular Toxicology
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    • v.2 no.4
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    • pp.279-284
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    • 2006
  • This paper describes the fabrication methods of a carbon nanotube (CNT) filter and a microdialysis chip. A CNT filter can help perform dialysis on a microfluidic chip. In this study, a membrane type of a CNT filter is fabricated and located in a microfluidic chip. The filter plays a role of a dialysis membrane in a microfluidic chip. In the fabrication process of a CNT filter, individual CNTs are entangled each other by amide bonding that is catalyzed by 1-Ethyl-3-(3-dimethylaminopropyl)carbodiimide (EDC) and N-hydroxysuccinimide (NHS). The chemically treated CNTs are shaped to form a CNT filter using a PDMS film-mold and vacuum filtering. Then, the CNT filter is sandwiched between PDMS substrates, and they are bonded together using a thin layer of PDMS prepolymer as adhesive. The PDMS substrates are fabricated to have a microchannel by standard photo-lithography technique.

Two-dimensional Chip-load Analysis for Automatic Feedrate Adjustment (이송률 자동조정을 위한 2차원 칩로드 해석)

  • 배석형;고기훈;최병규
    • Korean Journal of Computational Design and Engineering
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    • v.5 no.2
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    • pp.155-167
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    • 2000
  • To be presented is two-dimensional chip-load analysis for cutting-load smoothing which is needed in unmanned machining and high speed machining of sculptured surfaces. Cutter-engagement angle and effective cutting depth are defined as chip-loads which are the geometrical measures corresponding to cutting-load while machining. The extreme values of chip-loads are geometrically derived in the line-line and line-arc-line blocks of the two-dimensional NC-codes. AFA(automatic feedrate adjustment) strategy for cutting-load smoothing is presented based on the chip-load trajectories.

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A Dynamic Programming Approach to Feeder Arrangement Optimization for Multihead-Gantry Chip Mounter (동적계획법에 의한 멀티헤드 겐트리형 칩마운터의 피더배치 최적화)

  • 박태형
    • Journal of Institute of Control, Robotics and Systems
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    • v.8 no.6
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    • pp.514-523
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    • 2002
  • Feeder arrangement is an important element of process planning for printed circuit board assembly systems. This paper newly proposes a feeder arrangement method for multihead-gantry chip mounters. The multihead-gantry chip mounters are very popular in printed circuit board assembly system, but the research has been mainly focused on single-head-gantry chip mounters. We present an integer programming formulation for optimization problem of multihead-gantry chip mounters, and propose a heuristic method to solve the large NP-complete problem in reasonable time. Dynamic programming method is then applied to feeder arrangement optimization to reduce the overall assembly time. Comparative simulation results are finally presented to verify the usefulness of the proposed method.

Light-Adaptive Vision System for Remote Surveillance Using an Edge Detection Vision Chip

  • Choi, Kyung-Hwa;Jo, Sung-Hyun;Seo, Sang-Ho;Shin, Jang-Kyoo
    • Journal of Sensor Science and Technology
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    • v.20 no.3
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    • pp.162-167
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    • 2011
  • In this paper, we propose a vision system using a field programmable gate array(FPGA) and a smart vision chip. The output of the vision chip is varied by illumination conditions. This chip is suitable as a surveillance system in a dynamic environment. However, because the output swing of a smart vision chip is too small to definitely confirm the warning signal with the FPGA, a modification was needed for a reliable signal. The proposed system is based on a transmission control protocol/internet protocol(TCP/IP) that enables monitoring from a remote place. The warning signal indicates that some objects are too near.

SAPS의 탄소원 공급을 위한 유기물 연구

  • 이지은;고주인;김선준;유상희
    • Proceedings of the Korean Society of Soil and Groundwater Environment Conference
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    • 2004.09a
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    • pp.231-234
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    • 2004
  • The experiments on some organic materials used in SAPS are carried out for the better sulfate reduction efficiency and the longer lifetime. Organic materials include spent mushroom compost, sewage sludge, oak chip compost and the combination of there. Reactors with mushroom compost, sewage sludge, the mixture of mushroom compost and sewage sludge, and the mixture of mushroom compost and oak chip compost maintained pH higher than 6.0. Reactors with mushroom compost, the mixture of mushroom compost and sewage sludge, and the mixture of mushroom compost and oak chip compost maintained reduction condition. Reactors with sewage sludge, oak chip compost and the mixture of sewage and oak chip compost produced COD less than 2,000ppm. Reactors with sewage and the mixture of mushroom compost, sewage sludge, oak chip compost showed about 60% of sulfate removal ratios.

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Feasibility Study for a Lab-chip Development for LAL Test (LAL 시험용 Lab-chip 개발을 위한 타당성 연구)

  • 황상연;최효진;서창우;안유민;김양선;이은규
    • KSBB Journal
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    • v.18 no.5
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    • pp.429-433
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    • 2003
  • LAL (Limulus amebocyte lysate) test to detect and quantity endotoxin is based on gellation reaction between endotoxin and LAL from a blood extract of Limulus polyphemus. The test is labor intensive requiring dedicated personnel, takes relatively long reaction time (approximately 1 hr), requires relatively large volume of samples and reagents, and its end-point detection method is rather subjective. To solve these problems, we attempted to develop a miniaturized LOC (lab-on-a-chip) prototype using PDMS and glass. Using the 62 mm (length) ${\times}$ 18 mm (width) prototype in which 2 mm (width) ${\times}$ 44.34 mm (length) ${\times}$ 100 $\mu\textrm{m}$ (depth) microfluidic channel was provided, we compared the various detection methods of gellation, turbidometric, and chromogenic assays to find the chromogenic method to be the most suitable for small volume assay. In this assay, kinetic point method was more accurate than end point method. We also found the PDMS chip thickness should be minimized to around 2 mm to allow sufficient light transmittance, which necessitated a glass slide bonding for chip rigidity. Through the miniaturization, the test time was reduced from 1 hr to less than 10 minutes, and the sample volume could be reduced from 100 ${\mu}\ell$ to 4.4 ${\mu}\ell$. In sum, this study revealed that the mini LOC could be an alternative for a semi-automated and reliable method for LAL test.