• The Journal of the Acoustical Society of Korea
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• v.23 no.4E
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• pp.108-111
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• 2004

This paper has interest in the effect of a fine frequency offset, defined in ITU-T G.225, to the training performance of an adaptive equalizer. This paper uses Hilbert filter in configuring a transmission system model in order to let it get a frequency offset. Also additive white Gaussian noise and band-limited filter are considered. The signal received from the above transmission system applies to an adaptive equalizer with LMS algorithm, and its training procedures are investigated. As a result, we could find that even small fine frequency offset can severely deteriorate training performance of adaptive algorithm.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.11
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• pp.1074-1080
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• 2013

The low phase noise and wideband frequency synthesizer has been designed by using YTO. Offset PLL structure is used for reducing a division ratio of feedback loop. The phase noise modeling is applied to optimize loop filter of PLL and YTO module. And DDS is used as reference signal of frequency synthesizer for fine resolution. The fabricated wideband frequency synthesizer has the output frequency of 3.2 GHz to 6.8 GHz, phase noise of -107 dBc/Hz at 10 kHz offset from the carrier and frequency resolution of 1 Hz. The measured phase noise is well agreed with the simulated one.

• Journal of Industrial Technology
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• v.22 no.B
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• pp.133-139
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• 2002

In precision instrumentation system, an A/D conversion of signal conditioning has been always suffered from some problems ; offset and drift voltage with environmental situation. This paper suggests a method of reducing the offset voltage and the drift error from the A/D conversion hardware using analog signal switching technique with specific operational amplifier circuits. Also, we have designed a hardware active filter and a software digital filter with Auto Zero Tracking algorithm for better dignal process of the our proposed weighing system. Software technique was performed to obtain the stable data from A/D converter. As a result of our experimental works, the proposed system is expected to be used in the industrial field where a high precision measurement is required.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.65 no.1
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• pp.18-24
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• 2016

In order to service restoration and enhance power system reliability, a number of impedance based fault location algorithms have been developed for fault locating in a transmission line. This paper presents an advanced impedance-based fault location algorithms in a two-ended sources transmission line to reduce the DC offset error effects. This fault location algorithm uses of the GPS time synchronized voltage and current signals from the local and remote terminal. The algorithm uses an advanced DC offset removal filter. A series of test results using ATPdraw simulation data show the performance effectiveness of the proposed algorithm. The proposed algorithm is valid for a two-end sources transmission network.

• Proceedings of the KIEE Conference
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• 2002.11c
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• pp.301-304
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• 2002

This paper has been studied an A/D conversion system for precision weighing signal process In weighing system. A/D conversion has some problem.; offset drift voltage with environment situation and nonzero value of initial output voltage. The Offset voltage in analog circuit produces a drift of an output voltage before A/D conversion stage. This paper suggested the method of reducing the offset voltage by switching analog chopping circuit and making the initial output close to zero to enhance the swing range by D/A converter. Also, we have designed active filter and digital filter with Auto Zero Tracking algorithm for better signal process of the weighing system.

• Proceedings of the KIEE Conference
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• 2007.10a
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• pp.483-484
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• 2007

In this paper, we describe a chip design technique for instrumentation amplifier using a nested-chopping technique. Conventional chopping technique uses a pair of chopper, but nested chopping technique uses two pairs of chopper to reduce residual offset and 1/f noise. The inner chopper pair removes the 1/f noise, while the outer chopper pair reduces the residual offset. Our instrumentation amplifier using a nested chopping technique has residual offset under 100 nV. We also implement very low frequency filter. Since this filter needs very large RC time constant, we use a technique named 'diode connected PMOS' to increase R with small die area. The total power consumption is 3.1 mW at the supply voltage of 3.3V with the 0.35um general CMOS technology. The die area of implemented chip was $530um{\times}300um$.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.30 no.1
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• pp.28-37
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• 2016

Fault locating is an important element to minimize the damage of power system. The computation error of fault locator may occur by the influence of the DC offset component during phasor extraction. In order to minimize the bad effects of DC offset component, this paper presents an improved fault location algorithm based on a DC offset removal filter for short fault in a double circuit transmission line. We have modeled a 154kV double circuit transmission line by the ATP software to demonstrate the effectiveness of the proposed fault locating algorithm. The line to line short faults were simulated and then collected simulation data was used. It can be seen that the error rate of fault locating estimation by the proposed algorithm decreases than the error rate of fault locating estimation by conventional algorithm.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.20 no.3
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• pp.455-464
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• 2019

The sensorless control based on the flux linkage of PM synchronous motors has excellent position estimation characteristics at low speeds. However, a limitation arises because the integrator of flux estimator is saturated by the DC offset generated during the analog to digital conversion(ADC) process of the measured current. In order to overcome this limitation, HPF with a low cutoff frequency is used. However, the estimation performance is deteriorated (Ed- the verb deteriorate already includes the meaning of 'problem') at high speed due to the low cutoff frequency, and increasing the cutoff frequency of the HPF induces further problems of phase leading and initial starting failure at low speeds. In this paper, the cutoff frequency of HPF was synchronized to the operation frequency of the motor: at low speeds the cutoff frequency was set to low in order to reduce the phase leading of the estimated flux, and at high speeds it was set to high to raise the DC offset removal performance. As a result, the operating range was increased by 200%. Furthermore, a phase compensation algorithm is proposed to reduce the phase leading of the HPF to less than 1.5 degrees over the full operating range. The proposed sensorless control algorithm was verified by experiment with a PM synchronous motor for a washing machine.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.64 no.4
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• pp.291-296
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• 2015

Transmission line is exposed to a large area, and then faults are likely to occur than the other component of power system. When a fault occurs on a transmission line, fault locator helps fast recovery of power supply on power system. This paper deals with the design of a digital fault locator for improvement accuracy of the fault distance estimation and a fault occurrence position for transmission line. The algorithm of a fault locator uses a DC offset removal filter and DFT filter. The algorithm utilizes a fault data of GPS time synchronized. The computed fault information is transmitted to the other side substation through communication. The digital fault locator includes MPU module, ADPU module, SIU module, and a power module. The MMI firmware and software of the fault locator was implemented.

• ETRI Journal
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• v.32 no.3
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• pp.380-389
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• 2010

This paper presents a new edge-protection algorithm and its very large scale integration (VLSI) architecture for block artifact reduction. Unlike previous approaches using block classification, our algorithm utilizes pixel classification to categorize each pixel into one of two classes, namely smooth region and edge region, which are described by the edge-protection maps. Based on these maps, a two-step adaptive filter which includes offset filtering and edge-preserving filtering is used to remove block artifacts. A pipelined VLSI architecture of the proposed deblocking algorithm for HD video processing is also presented in this paper. A memory-reduced architecture for a block buffer is used to optimize memory usage. The architecture of the proposed deblocking filter is verified on FPGA Cyclone II and implemented using the ANAM 0.25 ${\mu}m$ CMOS cell library. Our experimental results show that our proposed algorithm effectively reduces block artifacts while preserving the details. The PSNR performance of our algorithm using pixel classification is better than that of previous algorithms using block classification.