• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.427-427
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• 2012

Ferroelectric-gate field effect transistor based memory using a nanowire as a conducting channel offers exceptional advantages over conventional memory devices, like small cell size, low-voltage operation, low power consumption, fast programming/erase speed and non-volatility. We successfully fabricated ferroelectric nonvolatile memory devices using both n-type and p-type Si nanowires coated with organic ferroelectric poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] via a low temperature fabrication process. The devices performance was carefully characterized in terms of their electrical transport, retention time and endurance test. Our p-type Si NW ferroelectric memory devices exhibit excellent memory characteristics with a large modulation in channel conductance between ON and OFF states exceeding $10^5$; long retention time of over $5{\times}10^4$ sec and high endurance of over 105 programming cycles while maintaining ON/OFF ratio higher $10^3$. This result offers a viable way to fabricate a high performance high-density nonvolatile memory device using a low temperature fabrication processing technique, which makes it suitable for flexible electronics.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 제37회 하계학술대회 논문집 C
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• pp.1426-1427
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• 2006

Chalcogenide based phase-change memory has a high capability and potential for the next generation nonvolatile memory device. Fast writing speed, low writing voltage, high sensing margin, low power consume and long cycle of read/write repeatability are also good advantages of nonvolatile phase-change memory. We have been investigated the new material for the phase-change memory. Its composition is consists of chalcogenide $Ge_{1}Se_{1}Te_2$ material. We made this new material to solve problems of conventional phase-change memory which has disadvantage of high power consume and high writing voltage. In the present work, we are manufactured $Ge_{1}Se_{1}Te_{2}/Ge_{2}Sb_{2}Te_{5}/Ge_{1}Se_{1}Te_{2}$ and $Ge_{2}Sb_{2}Te_{5}/Ge_{1}Se_{1}Te_{2}/Ge_{2}Sb_{2}Te_{5}$ sandwich triple layer structure devices are manufactured to investigate its electrical properties. Through the present work, we are willing to ensure a potential of substitutional method to overcome a crystallization problem on PRAM device.

• 한국재료학회지
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• 제19권9호
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• pp.462-467
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• 2009

The Charge Trap Flash (CTF) memory device is a replacement candidate for the NAND Flash device. In this study, Pt/$Al_2O_3/La_2O_3/SiO_2$/Si multilayer structures with lanthanum oxide charge trap layers were fabricated for nonvolatile memory device applications. Aluminum oxide films were used as blocking oxides for low power consumption in program/erase operations and reduced charge transports through blocking oxide layers. The thicknesses of $SiO_2$ were from 30 $\AA$ to 50 $\AA$. From the C-V measurement, the largest memory window of 1.3V was obtained in the 40 $\AA$ tunnel oxide specimen, and the 50 $\AA$ tunnel oxide specimen showed the smallest memory window. In the cycling test for reliability, the 30 $\AA$ tunnel oxide sample showed an abrupt memory window reduction due to a high electric field of 9$\sim$10MV/cm through the tunnel oxide while the other samples showed less than a 10% loss of memory window for $10^4$ cycles of program/erase operation. The I-V measurement data of the capacitor structures indicated leakage current values in the order of $10^{-4}A/cm^2$ at 1V. These values are small enough to be used in nonvolatile memory devices, and the sample with tunnel oxide formed at $850^{\circ}C$ showed superior memory characteristics compared to the sample with $750^{\circ}C$ tunnel oxide due to higher concentration of trap sites at the interface region originating from the rough interface.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권3호
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• pp.170-172
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• 2002

The epilayer of vertically stacked, self-assembled InAs Quantum Dots (QDs)was grown by MBE with solid sources in non-cracking K-cells, and the sample was fabricated to a FET structure using a conventional technology. The device characteristic and performance were studied. At 77K and room temperature, the threshold voltage shift values are 0.75V and 0.35 V, which are caused by the trapping and detrapping of electrons in the quantum dots. Discharging and charging curves form the part of a hysteresis loop to exhibit memory function. The electrical injection of confined electrons in QDs products the threshold voltage shift and memory function with the persistent electron trapping, which shows the potential use for a room temperature application.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.440-440
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• 2011

We report on the non-volatile memory characteristics of a bistable organic memory (BOM) device with Au nanoparticles (NPs) embedded in a conducting poly N-vinylcarbazole (PVK) colloids hybrid layer deposited on flexible polyethylene terephthalate (PET) substrates. Transmission electron microscopy (TEM) images show the Au nanoparticles distributed isotropically around the surface of a PVK colloid. The average induced charge on Au nanoparticles, estimated using the C-V hysteresis curve, was large, as much as 5 holes/NP at a sweeping voltage of ${\pm}3$ V. The maximum ON/OFF ratio of the current bistability in the BOM devices was as large as $1{\times}105$. The cycling endurance tests of the ON/OFF switching exhibited a high endurance of above $1.5{\times}105$ cycles and a high ON/OFF ratio of ~105 could be achieved consistently even after quite a long retention time of more than $1{\times}106$ s.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.281.2-281.2
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• 2016

Two-dimensional van der Waals (2D vdWs) materials have been extensively studied for future electronics and materials sciences due to their unique properties. Among them, black phosphorous (BP) has shown infinite potential for various device applications because of its high mobility and direct narrow band gap (~0.3 eV). In this work, we demonstrate a few-nm thick BP-based nonvolatile memory devices with an well-known poly(vinylidenefluoride-trifluoroethylene) [P(VDF-TrFE)] ferroelectric polymer gate insulator. Our BP ferroelectric memory devices show the highest linear mobility value of $1159cm^2/Vs$ with a $10^3$ on/off current ratio in our knowledge. Moreover, we successfully fabricate the ferroelectric complementary metal-oxide-semiconductor (CMOS) memory inverter circuits, combined with an n-type $MoS_2$ nanosheet transistor. Our memory CMOS inverter circuits show clear memory properties with a high output voltage memory efficiency of 95%. We thus conclude that the results of our ferroelectric memory devices exhibit promising perspectives for the future of 2D nanoelectronics and material science. More and advanced details will be discussed in the meeting.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제43회 하계 정기 학술대회 초록집
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• pp.318-318
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• 2012

A graphene layer is most important materials in resent year to enhance the electrical properties of semiconductor device due to high mobility, flexibility, strong mechanical resistance and transparency[1,2]. The resistance switching memory with the graphene layer have been reported for next generation nonvolatile memory device[3,4]. Also, the graphene layer is able to improve the electrical properties of memory device because of the high mobility and current density. In this study, the resistance switching memory device with metal-oxide nano-particles embedded in polyimide layer on the graphene mono-layer were fabricated. At first, the graphene layer was deposited $SiO_2$/Si substrate by using chemical vapor deposition. Then, a biphenyl-tetracarboxylic dianhydride-phenylene diamine poly-amic-acid was spin coated on the deposited metal layer on the graphene mono-layer. Then the samples were cured at $400^{\circ}C$ for 1 hour in $N_2$ atmosphere after drying at $135^{\circ}C$ for 30 min through rapid thermal annealing. The deposition of aluminum layer with thickness of 200 nm was done by a thermal evaporator. The electrical properties of device were measured at room temperature using an HP4156a precision semiconductor parameter analyzer and an Agilent 81101A pulse generator. We will discuss the switching mechanism of memory device with metal-oxide nano-particles on the graphene mono-layer.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.189-190
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• 2008

The electrical characteristics of band-gap engineered tunneling barriers consisting of thin $SiO_2$ and $Si_3N_4$ dielectric layers were investigated. The band structure of stacked tunneling barriers was studied and the effectiveness of these tunneling barriers was compared with that of the conventional tunneling barrier. The band-gap engineered tunneling barriers show the lower operation voltage, faster speed and longer retention time than the conventional $SiO_2$ tunnel barrier. The thickness of each $SiO_2$ and $Si_3N_4$ layer was optimized to improve the performance of non-volatile memory.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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• pp.20-20
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• 2007

Nanowire-based field-effect transistors (FETs) decorated with nanoparticles have been greatly paid attention as nonvolatile memory devices of next generation due to their excellent transportation ability of charge carriers in the channel and outstanding capability of charge trapping in the floating gate. In this work, top-gate single ZnO nanowire-based FETs with and without Au nanoparticles were fabricated and their memory effects were characterized. Using thermal evaporation and rapid thermal annealing processes, Au nanoparticles were formed on an $Al_2O_3$ layer which was semi cylindrically coated on a single ZnO nanowire. The family of $I_{DS}-V_{GS}$ curves for the double sweep of the gate voltage at $V_{DS}$ = 1 V was obtained. The device decorated with nanoparticles shows giant hysterisis loops with ${\Delta}V_{th}$ = 2 V, indicating a significant charge storage effect. Note that the hysterisis loops are clockwise which result from the tunneling of the charge carriers from the nanowire into the nanoparticles. On the other hand, the device without nanoparticles shows a negligible countclockwise hysterisis loop which reveals that the influence of oxide trap charges or mobile ions is negligible. Therefore, the charge storage effect mainly comes from the nanoparticles decorated on the nanowire, which obviously demonstrates that the top-gate single ZnO nanowire-based FETs decorated with Au nanoparticles are the good candidate for the application in the nonvolatile memory devices of next generation.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.298.1-298.1
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• 2016

Two-dimensional materials have been received significant interest after the discovery of graphene due to their fascinating electronic and optical properties for the application of novel devices. However, graphene lack of certain bandgap which is essential requirement to achieve high performance field-effect transistors. Analogous to graphene materials, molybdenum disulfide ($MoS_2$) as one of transition-metal dichalcogenides family presents considerable bandgap and exhibits promising physical, chemical, optical and mechanical properties. Here we studied nonvolatile memory based on $MoS_2$ which is grown by chemical vapor deposition (CVD) method. $MoS_2$ growth was taken on $1.5{\times}1.5cm^2$ $SiO_2$/Si-substrate. The samples were analyzed by Raman spectroscopy, atomic force microscopy and X-ray photoelectron spectroscopy. Current-voltage (I-V) characteristic was carried out HP4156A. The CVD-$MoS_2$ was analyzed as few layers and 2H-$MoS_2$ structure. From I-V measurement for two metal contacts on CVD-$MoS_2$ sample, we found typical resistive switching memory effect. The device structures and the origin of nonvolatile memory effect will be discussed.