• Transactions on Electrical and Electronic Materials
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• v.15 no.1
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• pp.16-19
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• 2014

Charge trapping nonvolatile memory capacitors with $ZrO_2$ as charge trapping layer were fabricated, and the effects of post annealing atmosphere ($NH_3$ and $N_2$) on their memory storage characteristics were investigated. It was found that the memory windows were improved, after annealing treatment. The memory capacitor after $NH_3$ annealing treatment exhibited the best electrical characteristics, with a 6.8 V memory window, a lower charge loss ~22.3% up to ten years, even at $150^{\circ}C$, and excellent endurance (1.5% memory window degradation). The results are attributed to deep level bulk charge traps, induced by using $NH_3$ annealing.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.911-913
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• 2008

In this work, nonvolatile memory (NVM) devices for system on panel of flat panel display (FPD) were fabricated using low temperature polycrystalline silicon (LTPS) thin film transistor (TFT) technology with an oxide-nitride-oxynitride (ONOn) stack structure on glass. The results demonstrate that the NVM devices fabricated using the ONOn stack structure on glass have suitable switching characteristics for data storage with a low operating voltage, a threshold voltage window of more than 1.8 V between the programming and erasing (P/E) states after 10 years and its initial threshold voltage window (${\Delta}V_{TH}$) after $10^5$ P/E cycles.

• Electrical & Electronic Materials
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• v.9 no.8
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• pp.789-798
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• 1996

The double nitride layer Metal Nitride Oxide Semiconductor(MNOS) structures were fabricated by variating both gas ratio and nitride thickness, and by duplicating nitride deposited and one nitride layer MNOS structure to improve nonvolatile memory characteristics of MNOS structures by Low Pressure Chemical Vapor Deposition(LPCVD) method. The nonvolatile memory characteristics of write-in, erase, memory retention and degradation of Bias Temperature Stress(BTS) were investigated by the homemade automatic .DELTA. $V_{FB}$ measuring system. In the trap density double nitride layer structures were higher by 0.85*10$^{16}$ $m^{-2}$ than one nitride layer structure, and the AVFB with oxide field was linearly increased. However, one nitride layer structure was linearly increased and saturated above 9.07*10$^{8}$ V/m in oxide field. In the erase behavior, the hole injection from silicon instead of the trapped electron emission was observed, and also it was highly dependent upon the pulse amplitude and the pulse width. In the memory retentivity, double nitrite layer structures were superior to one nitride layer structure, and the decay rate of the trapped electron with increasing temperature was low. At increasing the number on BTS, the variance of AVFB of the double nitride layer structures was smaller than that of one nitride layer structure, and the trapped electron retention rate was high. In this paper, the double nitride layer structures were turned out to be useful in improving the nonvolatile memory characteristics.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.2
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• pp.87-95
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• 2016

Nonvolatile memory (NVM) is being considered as an alternative of traditional memory devices such as SRAM and DRAM, which suffer from various limitations due to the technology scaling of modern integrated circuits. Although NVMs have advantages including nonvolatility, low leakage current, and high density, their inferior write performance in terms of energy and endurance becomes a major challenge to the successful design of NVM-based memory systems. In order to overcome the aforementioned drawback of the NVM, extensive research is required to develop energy- and endurance-aware optimization techniques for NVM-based memory systems. However, researchers have experienced difficulty in finding a suitable simulation tool to prototype and evaluate new NVM optimization schemes because existing simulation tools do not consider the feature of NVM devices. In this article, we introduce a NVM-based cache simulator to support rapid prototyping and evaluation of NVM-based caches, as well as energy- and endurance-aware NVM cache optimization schemes. We demonstrate that the proposed NVM cache simulator can easily prototype PRAM cache and PRAM+STT-RAM hybrid cache as well as evaluate various write traffic reduction schemes and wear leveling schemes.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.210-213
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• 2004

The phase transition between amorphous and crystalline states in chalcogenide semiconductor films can controlled by electric pulses or pulsed laser beam; hence some chalcogenide semiconductor films can be applied to electrically write/erase nonvolatile memory devices, where the low conductive amorphous state and the high conductive crystalline state are assigned to binary states. Memory switching in chalcogenides is mostly a thermal process, which involves phase transformation from amorphous to crystalline state. The nonvolatile memory cells are composed of a simple sandwich (metal/chalcogenide/metal). It was formed that the threshold voltage depends on thickness, electrode distance, annealing time and temperature, respectively.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.19-19
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• 2008

We investigated the programmable memory characteristics of nanoparticle-based memory devices based on the elementary metal nanoparticles (Co and Au) and their binary mixture synthesized by a micellar route to ordered arrays of metal nanoparticles as charge trapping layers. According to the metal nanoparticle species quite different programming/erasing efficiencies were observed, resulting in the tunable memory characteristics at the same programming/erasing bias conditions. This finding will be a good implication for further device scaling and novel device applications since most processes are based on the conventional semiconductor processes.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.31-32
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• 2010

In our previous reports [1-3], electron transport for the switching and memory devices using alkyl thiol-tethered Ru-terpyridine complex compounds with metal-insulator-metal crossbar structure has been presented. On the other hand, among organic memory devices, a memory based on the OFET is attractive because of its nondestructive readout and single transistor applications. Several attempts at nonvolatile organic memories involve electrets, which are chargeable dielectrics. However, these devices still do not sufficiently satisfy the criteria demanded in order to compete with other types of memory devices, and the electrets are generally limited to polymer materials. Until now, there is no report on nonvolatile organic electrets using nano-interfaced organic monomer layer as a dielectric material even though the use of organic monomer materials become important for the development of molecularly interfaced memory and logic elements. Furthermore, to increase a retention time for the nonvolatile organic memory device as well as to understand an intrinsic memory property, a molecular design of the organic materials is also getting important issue. In this presentation, we report on the OFET memory device built on a silicon wafer and based on films of pentacene and a SiO2 gate insulator that are separated by organic molecules which act as a gate dielectric. We proposed push-pull organic molecules (PPOM) containing triarylamine asan electron donating group (EDG), thiophene as a spacer, and malononitrile as an electron withdrawing group (EWG). The PPOM were designed to control charge transport by differences of the dihedral angles induced by a steric hindrance effect of side chainswithin the molecules. Therefore, we expect that these PPOM with potential energy barrier can save the charges which are transported to the nano-interface between the semiconductor and organic molecules used as the dielectrics. Finally, we also expect that the charges can be contributed to the memory capacity of the memory OFET device.[4]

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.192.1-192.1
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• 2015

We demonstrated the nonvolatile memory functionality of nano-crystalline silicon (nc-Si) and InGaZnOxide (IGZO) thin film transistors (TFTs) using mobile protons that are generated by very short time hydrogen neutral beam (H-NB) treatment in gate insulator (SiO2). The whole memory fabrication process kept under $50^{\circ}C$ (except SiO2 deposition process; $300^{\circ}C$). These devices exhibited reproducible hysteresis, reversible switching, and nonvolatile memory behaviors in comparison with those of the conventional FET devices. We also executed hydrogen treatment in order to figure out the difference of mobile proton generation between PECVD and H-NB CVD that we modified. Our study will further provide a vision of creating memory functionality and incorporating proton-based storage elements onto a probability of next generation flexible memorable electronics such as low power consumption flexible display panel.

• Electronics and Telecommunications Trends
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• v.35 no.3
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• pp.55-65
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• 2020

With the development of nonvolatile memory technology, Intel has released the Optane datacenter persistent memory module (DCPMM) that can be deployed in the dual in-line memory module. The results of research and experiments on Optane DCPMMs are significantly different from the anticipated results in previous studies through emulation. The DCPMM can be used in two different modes, namely, memory mode (similar to volatile DRAM: Dynamic Random Access Memory) and app direct mode (similar to file storage). It has buffers in 256-byte granularity; this is four times the CPU (Central Processing Unit) cache line (i.e., 64 bytes). However, these properties are not easy to use correctly, and the incorrect use of these properties may result in performance degradation. Optane has the same characteristics of DRAM and storage devices. To take advantage of the performance characteristics of this device, operating systems and applications require new approaches. However, this change in computing environments will require a significant number of researches in the future.

• Journal of the Semiconductor & Display Technology
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• v.19 no.3
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• pp.61-67
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• 2020

This paper is to propose a hybrid memory adaptor using next-generation nonvolatile memory devices such as phase-change memory to improve the performance limitations of OpenStack-based object storage systems. The proposed system aims to improve the performance of the account and container servers for object metadata management. For this, the proposed system consists of locality-based dynamic page buffer, write buffer, and nonvolatile memory modules. Experimental results show that the proposed system improves the hit rate by 5.5% compared to the conventional system.