• Title/Summary/Keyword: nonbinary LDPC codes

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Design and Performance Analysis of Nonbinary LDPC Codes With Low Error-Floors (오류 마루 현상이 완화된 비이진 LDPC 부호의 설계 및 성능 분석 연구)

  • Ahn, Seok-Ki;Lim, Seung-Chan;Yang, Youngoh;Yang, Kyeongcheol
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.38C no.10
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    • pp.852-857
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    • 2013
  • In this paper we propose a design algorithm for nonbinary LDPC (low-density parity-check) codes with low error-floors. The proposed algorithm determines the nonbinary values of the nonzero entries in the parity-check matrix in order to maximize the binary minimum distance of the designed nonbinary LDPC codes. We verify the performance of the designed nonbinary LDPC codes in the error-floor region by Monte Carlo simulation and importance sampling over BPSK (binary phase-shift keying) modulation.

Nonbinary Multiple Rate QC-LDPC Codes with Fixed Information or Block Bit Length

  • Liu, Lei;Zhou, Wuyang;Zhou, Shengli
    • Journal of Communications and Networks
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    • v.14 no.4
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    • pp.429-433
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    • 2012
  • In this paper, we consider nonbinary quasi-cyclic low-density parity-check (QC-LDPC) codes and propose a method to design multiple rate codes with either fixed information bit length or block bit length, tailored to different scenarios in wireless applications. We show that the proposed codes achieve good performance over a broad range of code rates.

Efficient Parallel Block-layered Nonbinary Quasi-cyclic Low-density Parity-check Decoding on a GPU

  • Thi, Huyen Pham;Lee, Hanho
    • IEIE Transactions on Smart Processing and Computing
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    • v.6 no.3
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    • pp.210-219
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    • 2017
  • This paper proposes a modified min-max algorithm (MMMA) for nonbinary quasi-cyclic low-density parity-check (NB-QC-LDPC) codes and an efficient parallel block-layered decoder architecture corresponding to the algorithm on a graphics processing unit (GPU) platform. The algorithm removes multiplications over the Galois field (GF) in the merger step to reduce decoding latency without any performance loss. The decoding implementation on a GPU for NB-QC-LDPC codes achieves improvements in both flexibility and scalability. To perform the decoding on the GPU, data and memory structures suitable for parallel computing are designed. The implementation results for NB-QC-LDPC codes over GF(32) and GF(64) demonstrate that the parallel block-layered decoding on a GPU accelerates the decoding process to provide a faster decoding runtime, and obtains a higher coding gain under a low $10^{-10}$ bit error rate and low $10^{-7}$ frame error rate, compared to existing methods.

Challenges and Some New Directions in Channel Coding

  • Arikan, Erdal;Hassan, Najeeb ul;Lentmaier, Michael;Montorsi, Guido;Sayir, Jossy
    • Journal of Communications and Networks
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    • v.17 no.4
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    • pp.328-338
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    • 2015
  • Three areas of ongoing research in channel coding are surveyed, and recent developments are presented in each area: Spatially coupled low-density parity-check (LDPC) codes, nonbinary LDPC codes, and polar coding.