• Journal of the Semiconductor & Display Technology
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• v.22 no.3
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• pp.106-111
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• 2023

The importance of load-to-use latency has been highlighted as state-of-the-art computing cores adopt deep pipelines and high clock frequencies. The cascaded cache was recently proposed to reduce the access cycle of the L1 cache by utilizing differences in latencies among banks of the cache structure. However, this study assumes the cache is comprised of SRAM, making it unsuitable for direct application to non-volatile memory-based systems. This paper proposes a novel mechanism and structure for lowering dynamic energy consumption. It inserts monitoring logic to keep track of swap operations and write counts. If the ratio of swap operations to total write counts surpasses a set threshold, the cache controller skips the swap of cache blocks, which leads to reducing write operations. To validate this approach, experiments are conducted on the non-volatile memory-based cascaded cache. The results show a reduction in write operations by an average of 16.7% with a negligible increase in latencies.

• Journal of the Optical Society of Korea
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• v.20 no.1
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• pp.169-173
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• 2016

Terahertz (THz) generation by a GaP ridge waveguide with a collinear modal phase-matching scheme based on cascaded difference frequency generation (DFG) processes is theoretically analyzed. The cascaded Stokes interaction processes and the cascaded anti-Stokes interaction processes are investigated from coupled wave equations. THz intensities and quantum conversion efficiency are calculated. Compared with non-cascaded DFG processes, THz intensities from 11-order cascaded DFG processes are increased to 5.48. The quantum conversion efficiency of 177.9% in cascaded processes can be realized, exceeding the Manley-Rowe limit.

• Current Optics and Photonics
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• v.1 no.2
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• pp.138-142
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• 2017

Terahertz (THz) generation by periodically-poled $KTiOPO_4$ (PPKTP) with a quasi-phase-matching scheme based on cascaded difference frequency generation (DFG) processes is theoretically analyzed. The cascaded Stokes interaction processes and the cascaded anti-Stokes interaction processes are investigated from coupled wave equations. THz intensities and quantum conversion efficiency are calculated. Compared with non-cascaded DFG processes, THz intensities from 10-order cascaded DFG processes are increased to 5.53. The quantum conversion efficiency of 479.4% in cascaded processes, which exceeds the Manley-Rowe limit, can be realized.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.10B
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• pp.1785-1792
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• 2000

In this paper multi-rate non-recursive architecture for CIC(Cascaded Integrator-Comb) decimation filters with an arbitrary factor is proposed. The CIC filters are widely used in high speed wireless communication systems since they have multiplier-less and multi-rate low-power structure. Even conventional non-recursive CIC structure is multi-rate this architecture can be structured only in case of M-th power-of-two decimation factor. This paper proposes that muli-rate non-recursive CIC architecture can be structured with an any decimation factor of product form. Power consumption of the proposed architecture is compared with that of the conventional non-recursion architecture.

• Journal of Information Processing Systems
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• v.7 no.4
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• pp.595-612
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• 2011

Most organizations use performance appraisal system to evaluate the effectiveness and efficiency of their employees. In evaluating staff performance, performance appraisal usually involves awarding numerical values or linguistic labels to employees performance. These values and labels are used to represent each staff achievement by reasoning incorporated in the arithmetical or statistical methods. However, the staff performance appraisal may involve judgments which are based on imprecise data especially when a person (the superior) tries to interpret another person's (his/her subordinate) performance. Thus, the scores awarded by the appraiser are only approximations. From fuzzy logic perspective, the performance of the appraisee involves the measurement of his/her ability, competence and skills, which are actually fuzzy concepts that can be captured in fuzzy terms. Accordingly, fuzzy approach can be used to handle these imprecision and uncertainty information. Therefore, the performance appraisal system can be examined using Fuzzy Logic Approach, which is carried out in the study. The study utilized a Cascaded fuzzy inference system to generate the performance qualities of some University non-teaching staff that are based on specific performance appraisal criteria.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.29-38
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• 2009

In this paper, a high performance pipelined computing design of parallel multiplier-temporal buffer-parallel accumulator is present for the convolution-based non-cascaded architecture aiming at the real time Discrete Wavelet Transform(DWT) processing. The convolved multiplication of DWT would be reduced upto 1/4 by utilizing the filter coefficients symmetry and the up/down sampling; and it could be dealt with 3-5 times faster computation by LUT-based DA multiplication of multiple filter coefficients parallelized for product terms with an image data. Further, the reutilization of computed product terms could be achieved by storing in the temporal buffer, which yields the saving of computation as well as dynamic power by 50%. The convolved product terms of image data and filter coefficients are realigned and stored in the temporal buffer for the accumulated addition. Then, the buffer management of parallel aligned storage is carried out for the high speed sequential retrieval of parallel accumulations. The convolved computation is pipelined with parallel multiplier-temporal buffer-parallel accumulation in which the parallelization of temporal buffer and accumulator is optimize, with respect to the performance of parallel DA multiplier, to improve the pipelining performance. The proposed architecture is back-end designed with 0.18um library, which verifies the 30fps throughput of SVGA(800$\times$600) images at 90MHz.

• Journal of Power Electronics
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• v.17 no.1
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• pp.106-114
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• 2017

In this paper, the Selective Harmonic Mitigation-PWM (SHM-PWM) method is used in single-phase and three-phase Cascaded H-Bridge (CHB) inverters in order to fulfill different power quality standards such as EN 50160, CIGRE WG 36-05, IEC 61000-3-6 and IEC 61000-2-12. Non-equal DC link voltages are used to increase the degrees of freedom for the proposed SHM-PWM technique. In addition, it will be shown that the obtained solutions become continuous and without sudden changes. As a result, the look-up tables can be significantly reduced. The proposed three-phase modulation method can mitigate up to the 50th harmonic from the output voltage, while each switch has just one switching in a fundamental period. In other words, the switching frequency of the power switches are limited to 50 Hz, which is the lowest switching frequency that can be achieved in the multilevel converters, when the optimal selective harmonic mitigation method is employed. In single-phase mode, the proposed method can successfully mitigate harmonics up to the 50th, where the switching frequency is 150 Hz. Finally, the validity of the proposed method is verified by simulations and experiments on a 9-level CHB inverter.

• Journal of Power Electronics
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• v.17 no.3
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• pp.777-787
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• 2017

A new single phase half-bridge cascaded multilevel inverter based series active power filter (SAPF) is proposed. The main parts of the inverter are presented in detail. With the proposed inverter topology, any compensation voltage reference can be easily obtained. Therefore, the inverter acts as a harmonic source when the reference is a non-sinusoidal signal. A 31-level inverter based SAPF with the proposed topology, is manufactured and the voltage harmonics of the load connected to the point of common coupling (PCC) are compensated. There is no need for a parallel passive filter (PPF) since the main purpose of the paper is to represent the compensation capability of the SAPF without a PPF. It is aimed to compensate the voltage harmonics of the load fed by a non-sinusoidal supply using the proposed inverter. The validity of the proposed inverter based SAPF is verified by simulation as well as experimental study. The system efficiency is also measured in this study. Both simulation and experimental results show that the proposed multilevel inverter is suitable for SAPF applications.

• Proceedings of the KIPE Conference
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• 2017.07a
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• pp.445-446
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• 2017

In this paper, adaptive prefiltering method is proposed for reduction of dc-link ripple in cascaded NPC/H-bridge system. Under non-linear load such as electric machine or harmonically distorted conditions, dc-link capacitor voltage with harmonics is inevitable result. In terms of reducing dc-link ripple, prefiltering method combined low pass filter with multiple second order generalized integrator is proposed. Proposed prefiltering method effectively reduces harmonics of dc-link ripple and improves characteristic of THD, simulated by using MATLAB R2014a and PSIM 9.1.4.

• Proceedings of the KIPE Conference
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• 2016.11a
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• pp.79-80
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• 2016

상용차에서 사용되고 있는 기계식 에어컨 시스템은 엔진의 가동(주행 또는 공회전)에 의해 발생되는 에너지를 이용해 차량 실내온도를 유지시켜준다. 이러한 기계식 에어컨 시스템의 작동은 엔진 구동력의 일부를 사용하기 때문에 상용차의 연비와 큰 관련성 있다. 상용차는 하절기 작업대기, 차량 내 야간취침 등이 빈번해 운전자의 운행습관에 따라 연료 소비량이 증가하는 단점을 가지고 있다. 본 논문에서는 이러한 단점을 개선하고자 대형 상용차량이 정차중인 무시동 기간에도 일정 온도의 유지가 가능 하도록 4kW급 Cascaded 푸쉬-풀 컨버터와 전동식 압축기 구동용 인버터로 구성된 전력변환장치를 제안하였다.