• Proceedings of the IEEK Conference
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• 2003.07d
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• pp.1283-1286
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• 2003

Human can update the memory with new information not forgetting acquired information in the memory. ART(Adaptive Resonance Theory) does not need to change all information. The methodology of ART is followed. The ART updates the memory with the new information that is unknown if it is similar with the memorized information. On the other hand, if it is unknown information the ART adds it to the memory not updating the memory with the new one. This paper shows that ART is able to classify sensory information of a certain object. When ART receives new information of the object as an input, it searches for the nearest thing among the acquired information in the memory. If it is revealed that new information of the object has similarity with the acquired object, the model is updated to reflect new information to the memory. When new object does not have similarity with the acquired object, the model register the object into new memory

• Journal of KIISE
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• v.42 no.4
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• pp.427-433
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• 2015

The rapid advancement of computing technology has triggered the need for fast data I/O processing and high-performance storage technology. Next generation memory technology, which we refer to as new memory, is anticipated to be used for high-performance storage as they have excellent characteristics as a storage device with non-volatility and latency close to DRAM. This research proposes NTL (New memory Translation layer) as a technology to make use of new memory as storage. With the addition of NTL, conventional I/O is served with existing mature disk-based file systems providing compatibility, while new memory I/O is serviced through the NTL to take advantage of the byte-addressability feature of new memory. In this paper, we describe the design of NTL and provide experiment measurement results that show that our design will bring performance benefits.

• Journal of the Korea Society of Computer and Information
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• v.23 no.4
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• pp.81-88
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• 2018

In this paper, we present some problems with the Groupware Messenger functionality based on dot net 2.0 and implement a new design structure to solve them. They include memory leakage, slow processing, and client window memory crash. These problems resulted in the inconvenience of using instant messaging and the inefficient handling of office tasks. Therefore, in this paper, instant messaging functionality is implemented according to a new design architecture. The new system upgrades dot net 4.5 for clients and deploys the new features based on MQTT for the messenger server. We verify that the memory leak problem and client window memory crash issues have been eliminated on the system with the new messenger functionality. We measure the amount of time it takes to bind data to a set of messages and evaluate the performance, compared to a given system. Through this comparative evaluation, we can see that the new system is more reliable and performing.

• ETRI Journal
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• v.35 no.5
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• pp.808-818
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• 2013

Programmable memory built-in self-test (PMBIST) is an attractive approach for testing embedded memory. However, the main difficulties of the previous works are the large area overhead and low flexibility. To overcome these problems, a new flexible PMBIST (FPMBIST) architecture that can test both single-port memory and dual-port memory using various test algorithms is proposed. In the FPMBIST, a new instruction set is developed to minimize the FPMBIST area overhead and to maximize the flexibility. In addition, FPMBIST includes a diagnostic scheme that can improve the yield by supporting three types of diagnostic methods for repair and diagnosis. The experiment results show that the proposed FPMBIST has small area overhead despite the fact that it supports various test algorithms, thus having high flexibility.

• Journal of the Korean Society for Industrial and Applied Mathematics
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• v.7 no.1
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• pp.7-14
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• 2003

The main concern of this paper is to develop a new class of quasi-newton methods. These methods are intended for use whenever memory space is a major concern and, hence, they are usually referred to as limited memory methods. The methods developed in this work are sensitive to the choice of the memory parameter ${\eta}$ that defines the amount of past information stored within the Hessian (or its inverse) approximation, at each iteration. The results of the numerical experiments made, compared to different choices of these parameters, indicate that these methods improve the performance of limited memory quasi-Newton methods.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.50 no.4
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• pp.192-200
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• 2001

As the high density memory is widely used in the various applications, the need for reproduction of memory is increased. In this paper we propose an efficient fault diagnosis algorithm of linear order O(n) that enables the reproduction of memory. The new algorithm can distinguish various fault models and identify all the cells related to the faults. In addition, a new BIST architecture for fault diagnosis is developed. Using the new algorithm, fault diagnosis can be performed efficiently. And the performance evaluation with previous approaches proves the efficiency of the new algorithm.

• Vacuum Magazine
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• v.1 no.3
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• pp.4-8
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• 2014

Since the modern computer architecture was suggested by Von Neumann in 1945, computer has become inevitable for our life. This brilliant growth of computer has been led by device miniaturization trend, so called Moore's law. Especially, the explosive growth of memory devices such as DRAM and Flash have played key role in huge enlarging utilization of computer. However, abrupt increase of data used for many applications in big data era provoke the excessive energy consumption of data center which results from the inefficiency of conventional memory-storage hierarchy. As a solution, the application of new memory devices has been brought up for innovative memory-storage hierarchy. In this paper, the current development status and prospect of new memory devices will be discussed.

• The Journal of Information Technology and Database
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• v.1 no.2
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• pp.103-125
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• 1994

In this paper, we introduce a new main memory storage system called FLASH that is designed for real-time applications. The FLASH system is characterized by the memory residency of data and a new fast and dynamic hashing scheme called extendible chained bucket hashing. We compared the performance of the new hashing algorithm with other well-known ones. Also, we carried out an experiment to compare the overall performance of the FLASH system with a commercial one. Both comparison results show that the new hashing scheme and the FLASH system outperforms other competitives.

• International Journal of Human Ecology
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• v.14 no.2
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• pp.41-51
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• 2013

This study investigated how family capital was associated with the working memory of young school-aged children from immigrant families in the United States using the New Immigrant Survey. Family capital was identified as economic, human, cultural, and social capital, and children's working memory was measured by the Digit Span scores. Poisson regression analysis was used for examining the sample of 428 children from the New Immigrant Survey. Results indicated that cultural capital within the home was positively associated with the working memory of young school-aged children whereas economic, human, and social capital was not. Implications and limitations of the study are also discussed.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.825-828
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• 2005

In this paper, we propose a new nonvolatile unit memory cell and proposal peripheral circuit using the polymer material. Memory that relies on bistable behavior- having tow states associated with different resistances at the same applied voltage - has attracted much interest because of its nonvolatile properties. Such memory may also have other merits, including simplicity of structure and manufacturing, and the small size of memory cells. We have plotted the load line graphs for the use of a polymer memory character, hence we have designed in the band-gap reference shape of a write/erase drive, and then designed in the 2-stage differential amplifier shape of a sense amplifier in the consideration of a low current characteristic of a polymer memory cell. The simulation result shows that is has high gain about 80dB by sensing the very small current.