• Proceedings of the IEEK Conference
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• 2001.06a
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• pp.281-284
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• 2001

In this paper, we design the Sorting-Banyan network with an efficient buffer and sorting management schema that makes switch be capable of supporting delay sensitive as well as loss sensitive. The proposed switching network is remodeled that based on Batcher-banyan network that have eight input and output ports The structure of designed switching network is constructed of modified banyan network with 2-way routing paths and two plane sorting networks. we have analysed the maximum throughput of the switch, under the uniform random traffic load, the FIFO discipline has increased by about 11% when we compare the switching system with the input buffering system.

• The Transactions of the Korea Information Processing Society
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• v.7 no.4
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• pp.1073-1081
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• 2000

This paper proposes a new fault-tolerant technique for bitonic sorting networks which can be used for designing ATM switches based on Batcher-Banyan network. The main goal in this paper is to design a cost-effective fault-tolerant bitonic sorting network. In order to recover a fault, additional comparison elements and additional links are used. A Dynamic Redundant Bitonic Sorting (DRBS) network is based on the Dynamic Redundant network and can be constructed with several different variations. The proposed fault-tolerant sorting network offers high fault-tolerance; low time delays; maintenance of cell sequence; simple routing; and regularity and modularity.

• Journal of Biosystems Engineering
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• v.24 no.4
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• pp.325-334
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• 1999

The aim of this study was to present a groundwork for development of a sorting system of peeled garlics using machine vision. Images of various garlic samples such as sound, partially defective, discolored, rotten and un-peeled were obtained with a B/W machine vision system. Sorting factors which were based on normalized histogram and statistical analysis(STEPDISC Method) had good separability for various garlic samples. Bayes discriminant function and neural network sorting algorithms were developed with the sample images and were experimented on various garlic samples. It was showed that garlic samples could be classified by sorting algorithm with average sorting accuracies of 88.4% by Bayes discriminant function and 93.2% by neural network.

• Journal of Biosystems Engineering
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• v.20 no.4
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• pp.376-382
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• 1995

This study was intended to develop more reliable fruit sorting algorithm regardless of the feeding positions of fruits by using the neural network in which various information could be included as input data. Specific objectives of this study were to select proper input units in the neural network by investigating the features of input image, to analyze the sorting accuracy of the algorithm depending on the feeding positions of Fuji apple and to evaluate the performance of the algorithm for practical usage. the average value in color grading accuracy was 90%. Based on the computing time required for color grading, the maximum sorting capacity was estimated to approximately 10, 800 apples per hours. Finally, it is concluded that the neuro-net based color sorting algorithm developed in this study has feasibility for practical usage.

• Proceedings of the Korea Inteligent Information System Society Conference
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• 2006.06a
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• pp.303-310
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• 2006

The sorting algorithms have been developed to take advantage of distributed computers. But the speedup of parallel sorting algorithms decrease rapidly with increased number of processors due to parallel processing overhead such as context switching time and inter-processor communication cost. In this paper, we propose a parallel sorting method which provides linear speedup of an optimal serial algorithm for a system with a large number of processors. This algorithm may even provide superlinear speedup for a practical system. The algorithm takes advantage of an interconnection network properties and its protocol.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.7
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• pp.19-30
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• 1992

In this paper, a new large scale ATM switch architecture for Broadband ISDN is presented and its performance is analyzed mathematically. The proposed two-stage ATM switch consists of a sorting network and several unit switches. The proposed switch is self-routing and nonlocking. Its maximum through put is 100% without speed up which other output buffered switch needs. The hardware complexity mainly depends on that of a sorting network, but sorting network is easy to be implemented to VLSI because of its regularity in the structure.

• Agricultural and Biosystems Engineering
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• v.1 no.2
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• pp.100-105
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• 2000

Quality sorting of cut flowers is very essential to increase the value of products. There are many factors that determine the quality of cut flowers such as length, thickness, and straightness of stem, and color and maturity of bud. Among these factors, the straightness of stem and the maturity of bud are generally considered to be more difficult to evaluate. A prototype grading and sorting machine for cut flowers was developed and tested for a rose variety. The machine consisted of a chain-drive feed mechanism, a pneumatic discharge system, and a grading system utilizing color image processing and neural network. Artificial neural network algorithm was utilized to grade cut roses based on the straightness of stem and maturity of bud. Test results showed 89% agreement with human expert for the straightness of stem and 90% agreement for the maturity of bud. Average processing time for evaluating straightness of the stem and maturity of the bud were 1.01 and 0.44 second, respectively. Application of neural network eliminated difficulties in determining criteria of each grade category while maintaining similar level of classification error.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.8
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• pp.3641-3655
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• 2016

Wireless sensor networks (WSNs) provide a promising approach to monitor the physical environments, to prolong the network lifetime by exploiting the mutual correlation among sensor readings has become a research focus. In this paper, we design a hierarchical network framework which guarantees layered-compression. Meanwhile, a data sorting-based adaptive spatial compression scheme (DS-ASCS) is proposed to explore the spatial correlation among signals. The proposed scheme reduces the amount of data transmissions and alleviates the network congestion. It also obtains high compression performance by sorting original sensor readings and selectively discarding the small coefficients in transformed matrix. Moreover, the compression ratio of this scheme varies according to the correlation among signals and the value of adaptive threshold, so the proposed scheme is adaptive to various deploying environments. Finally, the simulation results show that the energy of sorted data is more concentrated than the unsorted data, and the proposed scheme achieves higher reconstruction precision and compression ratio as compared with other spatial compression schemes.

• Journal of Information Processing Systems
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• v.7 no.2
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• pp.271-286
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• 2011

In this paper, we propose efficient algorithms for parallel prefix computation and sorting on a recursive dual-net. The recursive dual-net $RDN^k$(B) for k > 0 has $(2n_o)^{2K}/2$ nodes and $d_0$ + k links per node, where $n_0$ and $d_0$ are the number of nod es and the node-degree of the base-network B, respectively. Assume that each node holds one data item, the communication and computation time complexities of the algorithm for parallel prefix computation on $RDN^k$(B), k > 0, are $2^{k+1}-2+2^kT_{comm}(0)$ and $2^{k+1}-2+2^kT_{comp}(0)$, respectively, where $T_{comm}(0)$ and $T_{comp}(0)$ are the communication and computation time complexities of the algorithm for parallel prefix computation on the base-network B, respectively. The algorithm for parallel sorting on $RDN^k$(B) is restricted on B = $Q_m$ where $Q_m$ is an m-cube. Assume that each node holds a single data item, the sorting algorithm runs in $O((m2^k)^2)$ computation steps and $O((km2^k)^2)$ communication steps, respectively.

• International Journal of Computer Science & Network Security
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• v.22 no.12
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• pp.197-204
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• 2022

Sorting is an important data structure in many applications in the real world. Several sorting algorithms are currently in use for searching and other operations. Sorting algorithms rearrange the elements of an array or list based on the elements' comparison operators. The comparison operator is used in the accurate data structure to establish the new order of elements. This report analyzes and compares the time complexity and running time theoretically and experimentally of insertion, merge, and heap sort algorithms. Java language is used by the NetBeans tool to implement the code of the algorithms. The results show that when dealing with sorted elements, insertion sort has a faster running time than merge and heap algorithms. When it comes to dealing with a large number of elements, it is better to use the merge sort. For the number of comparisons for each algorithm, the insertion sort has the highest number of comparisons.