• Journal of Positioning, Navigation, and Timing
• /
• v.6 no.3
• /
• pp.87-94
• /
• 2017

GNSS modernization and development is in progress throughout the globe, and it is focused on the addition of a new navigation signal. Accordingly, for the next-generation GNSS signals that have been developed or are under development, various combinations that are different from the existing GNSS signal structures can be introduced. In this regard, to design an advanced signal, it is essential to clearly understand the effects of the signal structure and design variables. In the present study, the effects of the GNSS spreading code period and GNSS data bit duration (i.e., signal design variables) on the signal processing performance were analyzed when the data bit transition was considered, based on selected GNSS signal design scenarios. In addition, a method of utilizing the obtained result for the design of a new GNSS signal was investigated.

• Journal of Advanced Navigation Technology
• /
• v.11 no.4
• /
• pp.388-393
• /
• 2007

In designing transform coders bit allocation is one of the important issues. In this paper we propose two optimal algorithms for integer bit allocation in transform coding. Based on high-resolution formulas for bit allocation, the most and least greedy algorithms are developed to optimally adjust non-integer bit rates of coefficient quantizers to integer values. In particular, a duality property is observed between the two greedy algorithms.

• Journal of Navigation and Port Research
• /
• v.29 no.10 s.106
• /
• pp.877-882
• /
• 2005

It is necessary that Fail-Safe Seaway technology providing a continuous navigation solution though fault of navigation system is occurred in sea. This paper focus on signal processing of GPS receiver, one of receivers using the software radio technology to implement a integrated radio navigation system including satellite-based and ground-based navigation systems. It is difficult to implement the software GPS receivers using a commercial processor because of the heavy computational burden for processing the GPS signals in real time. This paper proposes an efficient multi-bit GPS signal processing scheme to reduce the computational burden for processing the GPS signals in the software GPS receiver. The proposed scheme uses a compression concept of the multi-bit replica signals and patterned look-up table method to generate the correlation value between the GPS signals and the replica signals.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
• /
• 2005.10a
• /
• pp.37-42
• /
• 2005

It is necessary that Fail-Safe Seaway technology providing a continuous navigation solution though fault of navigation system is occurred in sea. This paper focus on signal processing of GPS receiver, one of receivers using the software radio technology to implement a integrated radio navigation system including satellite-based and ground-based navigation systems. It is difficult to implement the software GPS receivers using a commercial processor bemuse of the heavy computational burden for processing the GPS signals in real time. This paper proposes an efficient multi-bit GPS signal processing scheme to reduce the computational burden for processing the GPS signals in the software GPS receiver. The proposed scheme uses a compression concept of the multi-bit replica signals and patterned look-up table method to generate the correlation value between the GPS signals and the replica signals.

• Journal of Advanced Navigation Technology
• /
• v.15 no.4
• /
• pp.591-595
• /
• 2011

In this paper, we design the hardware architecture of the BICM(Bit Interleaved Coded Modulation) module for next generation European broadcast system and implement the BICM module with DSP(Digital Signal Processor) TMS320C6474. Simulation result shows that the BER(Bit Error Rate) performance of the fixed-point BICM module using more than 8 bits is very similar to that of the floating-point BICM module.

• Journal of Advanced Navigation Technology
• /
• v.6 no.3
• /
• pp.223-230
• /
• 2002

In this paper, we induced that the noise powers and bit error rate of direct detection receiver taking account of ISI (intersymbol interference) in the 2,000 km optical transmission system. And we evaluated the sensitivity in the vrious bit rate system. We verified that the proposed calculation method is applicable to the exact optical system. And we confirmed that the signal distortion due to both chromatic dispersion and nonlinear effects compensated by using of MSSI (Mid-Span Spectral Inversion) method, and yet the sensitivity of a higher bit rate system is reduced, because of the increase of ISI and then the decrease of the average receiving power, compared with a the lower bit rate system.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
• /
• v.1
• /
• pp.121-125
• /
• 2006

A new GPS receiver correlator for the deeply-coupled GPS/INS integration system is proposed in order to the computation time problem of the Kalman filter. The proposed correlator consists of two early, prompt and late arm pairs. One pair is for detecting data bit transition boundary and another is for the correlator value calculation between input and replica signal. By detecting the data bit transition boundary, the measurement calculation time can be made longer than data bit period. As a result of this, the computational time problem of the integrated Kalman filter can be resolved. The validity of the proposed method is given through computer simulations.

• Journal of Advanced Navigation Technology
• /
• v.9 no.2
• /
• pp.156-163
• /
• 2005

In this paper, we analyzed the performance of VDL mode 3 system model whose specification is defined by ICAO(International Civil Aviation Organization). For performance evaluation, we obtained BER(Bit Error Rate), transmission delay time, burst retransmission rate and throughput. From the analysis result, we could explicitly define relationships among BER, transmission delay time, throughput and burst restransmission rate. In addition, it became known that V/D retransmission rate and throughput are closely related in down link channel.

• Journal of Advanced Navigation Technology
• /
• v.14 no.2
• /
• pp.233-238
• /
• 2010

In this paper, we applied the forward and backward error recovery techniques to a reduced instruction set computer (risc) processor to develop two fault-tolerant processors, namely, fetch redundant risc (FRR) processor and a redundancy execute risc (RER) processor. To evaluate the fault-tolerance capability of three target processors, we developed the base risc processor, FRR processor, and RER processor in SystemC hardware description language. We performed fault injection experiment using the three SystemC processor models and the SystemC-based simulation fault injection technique. From the experiments, for the 1-bit transient fault, the failure rate of the FRR, RER, and base risc processor were 1%, 2.8%, and 8.9%, respectively. For the 1-bit permanent fault, the failure rate of the FRR, RER, and base risc processor were 4.3%, 6.5%, and 41%, respectively. As a result, for 1-bit fault, we found that the FRR processor is more reliable among three processors.

• Journal of Advanced Navigation Technology
• /
• v.11 no.4
• /
• pp.408-414
• /
• 2007

Research advances in the areas of micro-sensor device and wireless network technology, has made it possible to develop energy efficient and low cost wireless sensor nodes. In this paper, the forward error control (FEC) scheme for lower power consumption and excellent BER(Bit Error Rate) performance during transmission propose in multi-hop wireless sensor network based on FSK modem. The FEC technique uses extra processing power related to encoding and decoding, it is need complex functions to be built into the sensor node. The probability of receiving a correct bit and codeword for relaying a frame over h nodes to the sink node is calculated as a function of channel parameter, number of hops, number of bits transmitted and the distance between the different nodes.