• KIPS Transactions on Computer and Communication Systems
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• v.2 no.6
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• pp.237-244
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• 2013

We propose Energy-constrained Multiprocessor Real-Time Scheduling algorithms for (m,k)-firm deadline constrained tasks (EMRTS-MK). Rather than simply saving as much energy as possible, we consider energy as hard constraint under which the system remains functional and delivers an acceptable performance at least during the prescribed mission time. We evaluate EMRTS-MKs in several experiments, which quantitatively show that they achieve the scheduling objectives.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.2
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• pp.149-158
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• 1996

In this paper we describe designing and implementing a digital neural chip and a parallel neural machine for simulating large scale neural netsorks. The chip is a single-chip multiprocessor which has four digiral neural processors (DNP-II) of the same architecture. Each DNP-II has program memory and data memory, and the chip operates in MIMD (multi-instruction, multi-data) parallel processor. The DNP-II has the instruction set tailored to neural computation. Which can be sed to effectively simulate various neural network models including on-chip learning. The DNP-II facilitates four-way data-driven communication supporting the extensibility of parallel systems. The parallel neural machine consists of a host computer, processor boards, a buffer board and an interface board. Each processor board consists of 8*8 array of DNP-II(equivalently 2*2 neural chips). Each processor board acn be built including linear array, 2-D mesh and 2-D torus. This flexibility supports efficiency of mapping from neural network models into parallel strucgure. The neural system accomplishes the performance of maximum 40 GCPS(giga connection per second) with 16 processor boards.

• Journal of the Korea Society of Computer and Information
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• v.11 no.2 s.40
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• pp.35-42
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• 2006

In this paper we implement a new simulator for performance analysis of a parallel digital signal processing distributed shared memory multiprocessor systems. using Parsec The key idea of this simulator is suitable in simulation of system that uses DMA function of TMS320C6701 DSP chip and local memory which have fast access time. Also, because correction of performance parameter and reconfiguration for hardware components are easy, we can analyze performance of system in various execution environments. In the simulation, FET, 2D FET, Matrix Multiplication. and Fir Filter, which are widely used DSP algorithms. have been employed. Using our simulator, the result has been recorded according to different the number of processor, data sizes, and a change of hardware element. The performance of our simulator has been verified by comparing those recorded results.

• Proceedings of the Korean Information Science Society Conference
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• 2007.06a
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• pp.250-251
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• 2007

• 제어로봇시스템학회:학술대회논문집
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• 1993.10a
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• pp.276-280
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• 1993

An articulated, multifinger mechanical hand can carry out grasping and manipulation operations on objects of different type and shape. In this paper the architecture of the mechanical hand is presented. Joints are driven by two antagonist tendons. Strain gauges are used to derive tendon tensions, and located in the palm of the hand. Angular defection of the joints is measured by Hall effect sensors attached to the joints. A multiprocessor-based architecture for controlling the hand is illustrated.

• 제어로봇시스템학회:학술대회논문집
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• 1986.10a
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• pp.169-174
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• 1986

This thesis investigates the scanning time ; one of the most important performance index of Programmable Controller(PC). The multiprocessor architecture of the large PC considered in this thesis are classified as architecture 1 and architecture 2 by the bus control methods. The queuing model of each architecture is developed. Form the analysis it is observed that in the case of the number of processors less than 3 the best architecture of the large PC is the architecture 2 and in the case of the number of processors greater than 2 the best architecture of the large PC is the architecture 1.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.5
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• pp.1-9
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• 1993

In this paper, we develop enhanced hypercube architectures and routing algorithms to realize arbitrary permutations in circuit switching. We prove that a hypercube is rearrangeable if one additional pair of links (one full-duplex communication line) is provided in only one dimesion of connections. We also prove that if each connection between two neighboring nodes consists of two pairs of links, the hypercube can handle two independent permutations simultaneously.

• Proceedings of the Korean Information Science Society Conference
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• 2000.04a
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• pp.113-115
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• 2000

n개의 동일한 프로세서 상에서 m개의 주기적인 태스크들의 적합한 스케줄을 구하기 위한 알고리즘을 제시한다. 정수이하의 작은 시간으로 태스크의 실행시간이 잘라질 수 있다는 가정 하에 태스크 집합은 기본 스케줄링 알고리즘을 통해서 부분적인 스케줄을 얻고 정수 화를 위한 다중프로세서 스케줄링 알고리즘으로 적합한 스케줄을 구성한다. 또한 태스크들에 대한 활용도의 합이 n보다 작거나 같다는 조건은 실시간 다중프로세서 시스템에서 주기적인 태스크 집합에 대한 적합한 스케줄을 구성하기 위한 필요.충분조건임을 보여준다.

• Proceedings of the Korean Information Science Society Conference
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• 2003.04a
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• pp.97-99
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• 2003

대칭형 다중프로세서 (SMP: Symmetric Multiprocessors) 시스템은 고성능의 병렬 연산을 위한 중요하고 효과적인 기반환경을 제공하고 있다. SMP에서 태스크 클러스터링과 스케줄링 기법은 시스템의 성능에 큰 영향을 미친다. 본 논문에서는 버스 기반의 SMP에서 사용할 수 있는 태스크 중복 기반의 클러스터링과 스케줄링 기법을 소개한다. 본 논문에서 제안한 클러스터링 기법에서는 휴리스틱을 사용하여 중복할 태스크를 선택한 후 프로세서에 할당하고, 스케줄링 기법에서는 잠재하는 통신 충돌을 방지하기 위하여 네트워크 통신 자원을 사전에 할당한다. 새로운 클러스터링과 스케줄링 기법의 성능을 확인하기 위하여 시뮬레이션에서는 통신비용의 변화에 대한 병렬연산시간을 비교하였다.

• Proceedings of the Korean Information Science Society Conference
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• 2002.10c
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• pp.334-336
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• 2002

본 논문에서는 스타그래프 다중처리시스템을 위한 새로운 프로세서 할당방범을 제안한다. 기존의 할당방법은 프로세서 단편화로 인해 작업을 처리할 서브스타를 형성하지 못하면 프로세서 할당이 지연되는 문제점이 있었다. 이러한 할당 지연은 작업의 대기시간을 증가시키고 시스템의 성능 향상을 제한한다. 본 논문에서 제안하는 할당방법은 프로세서 할당 지연이 발생하면 동적할당테이블을 사용하여 단편화된 프로세서의 주소론 재생성한다. 새로운 주소의 프로세서들로 가용 서브스타를 형성하여 할당함으로써 작업의 대기시간을 줄이고 프로세서 단편화를 최소화한다.