• The KIPS Transactions:PartA
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• v.17A no.6
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• pp.259-264
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• 2010

In case of scheduling tasks with shared resources in multiprocessor systems, Global Earliest Deadline First (GEDF) algorithm, equally applied Earliest Deadline First (EDF) which runs scheduling with deadline criterion, makes schedulability decline because GEDF typically does not have a specific process in order to handle tasks with shared resources. In this paper, we propose Earliest Deadline First with Partitioning (EDFP) for tasks with shared resources which partitions a task into two kinds of subtasks that include critical sections to access to shared resources, gives their own deadline respectively and manages them. As a result of simulations, EDFP shows better performance than GEDF for tasks with shared resources since system load goes up and the number of processor increases.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.2
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• pp.351-356
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• 2015

Synthetic utilization on multiprocessor system is not considered periodic tasks, except scheduling methods for aperiodic tasks where one of the real-time aperiodic tasks is a scheduling method. But really aperiodic tasks scheduling method is composed of mixed task types. Aperiodic task scheduling method guarantee an analysis of the schedualibility of aperiodic task. The set of mixed tasks periodic and aperiodic tasks scheduling method uses improved synthetic utilization that is presented in this paper. The new method shows that schedulability increases aperiodic server method.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.4
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• pp.1889-1896
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• 2011

There has been a lot of researches to develop techniques that provide redundant paths, there by making Multistage Interconnection Networks(MINs) fault tolerant. So far, the redundant paths in MINs have been realized by adding additional hardware such as extra stages or duplicated data links. This paper presents a new MIN topology called Hierarchical MIN. The proposed MIN is constructed with 2.5N-4 switching elements, which are much fewer than that of the classical MINs. Even though there are fewer hardware than the classical MINs, the HMIN possesses the property of full access and also provides alternative paths for the fault tolerant. Furthermore, since there is the short cut in HMIN for the localized communication, it takes advantage of exploiting the locality of reference in multiprocessor systems. Its performance under varying degrees of localized communication is analysed and simulated.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.6
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• pp.3046-3070
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• 2017

Nowadays, the utilization of multiprocessor environments has been increased due to the increase in time complexity of application programs and decrease in hardware costs. In such architectures during the compilation step, each program is decomposed into the smaller and maybe dependent segments so-called tasks. Precedence constraints, required execution times of the tasks, and communication costs among them are modeled using a directed acyclic graph (DAG) named task-graph. All the tasks in the task-graph must be assigned to a predefined number of processors in such a way that the precedence constraints are preserved, and the program's completion time is minimized, and this is an NP-hard problem from the time-complexity point of view. The results obtained by different approaches are dominated by two major factors; first, which order of tasks should be selected (sequence subproblem), and second, how the selected sequence should be assigned to the processors (assigning subproblem). In this paper, a hybrid proposed approach has been presented, in which two different artificial ant colonies cooperate to solve the multiprocessor task-scheduling problem; one colony to tackle the sequence subproblem, and another to cope with assigning subproblem. The utilization of background knowledge about the problem (different priority measurements of the tasks) has made the proposed approach very robust and efficient. 125 different task-graphs with various shape parameters such as size, communication-to-computation ratio and parallelism have been utilized for a comprehensive evaluation of the proposed approach, and the results show its superiority versus the other conventional methods from the performance point of view.

• Journal of Korea Society of Industrial Information Systems
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• v.6 no.2
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• pp.38-46
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• 2001

This paper presents a new multiprocessor system and corresponding scheduling algorithm that can be applied for implementation of fine grain DSP algorithms such as digital filters. The newly proposed system uses one or more shared buses as the basic interconnection network between processors, and fixed amount of clock-skew is maintained between instruction execution of processors. This system not only can handle the interprocessor communications very efficiently but also can explicitly incorporate the interprocessor communication delay time into the multiprocessor scheduling model. This paper also presents a new scheduling strategy for implementing digital filters expressed in fully-specified flow graphs on the proposed system. The simulation result shows that well-known digital filters can be implemented on proposed multiprocessor in which the implementation satisfies the iteration period bound.

• Journal of Internet Computing and Services
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• v.6 no.6
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• pp.99-106
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• 2005

The task scheduling in multiprocessor system Is one of the key elements in the effective utilization of multiprocessor systems. The optimal assignment of tasks to multiprocessor is, in almost all practical cases, an NP hard problem. Consequently various modern heuristics based algorithms have been proposed for practical reason. Recently, several approaches using Genetic Algorithm (GA) are proposed. However, these algorithms have only one objective such as minimizing cost and makespan. This paper proposes a new task scheduling algorithm using Genetic Algorithm combined simulated annealing (GA+SA) on multiprocessor environment. In solution algorithms, the Genetic Algorithm (GA) and the simulated annealing (SA) are cooperatively used. In this method. the convergence of GA is improved by introducing the probability of SA as the criterion for acceptance of new trial solution. The objective of proposed scheduling algorithm is to minimize makespan and total number of processors used. The effectiveness of the proposed algorithm is shown through simulation studies. In simulation studies, the results of proposed algorithm show better than that of other algorithms.

• Journal of KIISE:Computer Systems and Theory
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• v.29 no.11
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• pp.611-621
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• 2002

For real-time systems, multiprocessor support is indispensable to handle the large number of requests. Existing real-time on-line scheduling algorithms such as Earliest Deadline First Algorithm (EDF) and Least Laxity Algorithm (LLA) may not be suitable for scheduling real-time tasks in multiprocessor systems. Although EDF has low context switching overhead, it suffers from "multiple processor anomalies." LLA has been shown as suboptimal, but has the potential for higher context switching overhead. Earliest Deadline Zero Laxity (EDZL) solved somewhat the problems of those algorithms, however is suboptimal for only two processors. Another algorithm EDA2 shows very good performance in overload phase, however, is not suboptimal for muitiprocessors. We propose two on-line scheduling algorithms, Earliest Deadline/Least Laxity (ED/LL) and ED2/LL. ED/LL is suboptimal for multiprocessors, and has low context switching overhead and low deadline miss rate in normal load phase. However, ED/LL is ineffective when the system is overloaded. To solve this problem, ED2/LL uses ED/LL or EDZL in normal load phase and uses EDA2 in overload phase. Experimental results show that ED2/LL achieves good performance in overload phase as wet] as in normal load phase.oad phase.

• IEMEK Journal of Embedded Systems and Applications
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• v.9 no.6
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• pp.315-321
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• 2014

Mobile computing devices such as smartphones, tablet computers have become the dominant personal computing platforms. Energy efficiency is a prime design requirement for smart devices. In order to reduce the energy consumption of the smart devices, analysis of performance and energy consumption has become important. However, so far, there is no framework for the analysis and systematic approach to improve the power consumption of the heterogeneous multi-core system. In this paper, we describe a new framework for the analysis of heterogeneous multi-core systems. Also, by use of an analysis tool, can be provide reliability and productivity of development results.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.431-432
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• 2008

We propose a DVS technique for multiprocessor systems considering the energy consumed when translating voltage. We schedule periodic applications on two identical processors throughout a three-stage process; firstly, the computation energy consumption is minimized then the number of voltage translations is minimized. Finally, the result is compared with the schedule with no voltage translation and the one with smaller energy consumption is chosen. Overall, 10.6% energy reduction was achieved.

• ETRI Journal
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• v.33 no.3
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• pp.407-414
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• 2011

In an effort to reduce energy consumption, research into adaptive power management in real-time systems has become widespread. In this paper, a novel dynamic voltage scaling scheme is proposed for multiprocessor systems. Based on the concept of the Nash bargaining solution, a processor's clock speed and supply voltage are dynamically adjusted to satisfy these conflicting performance metrics. In addition, the proposed algorithm is implemented to react adaptively to the current system conditions by using an adaptive online approach. Simulation results clearly indicate that the superior performance of the proposed scheme can strike the appropriate performance balance between contradictory requirements.