• Journal of the Korean Institute of Intelligent Systems
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• v.6 no.4
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• pp.3-9
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• 1996

본 논문에서는 Boole 함수를 기호 다치 논리 함수로 확장하여 법-M(Modulus-M)의 수체계를 기본으로 하는 기호 다치 논리 함수에 대한 MacLaurin 전개의 구조적 성질을 분석한다. 그리고 기호 다치 변수의 상태 변화에 따라 이에 사상된 퍼지 규칙을 자동 생성할 수 있는 기법을 제안한다. 또한 이러한 이론과 성질을 기존의 퍼지 추론 기능과 결합하여 동적인 상태 변화에 적응할 수 있는 퍼지 추론 시스템 설계방법을 제안한다.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1998.06a
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• pp.537-542
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• 1998

Logic functions such as fuzzy switching functions and multiple-valued Kleenean functions, that are models of Kleene algebra have been studied as foundation of fuzzy logic. This paper deals with a new kinds of functions-fuzzy switching functions with constants-which have features of both the above two kinds of functions . In this paper, we propose new canonical forms for enumerating them. They are much useful to estimate simply the number of fuzzy switching functions with constants.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2006.11a
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• pp.215-219
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• 2006

최근 유비쿼터스 컴퓨팅 환경에서 핵심적인 요소 기술인 상황인식 시스템을 실현하기 위해 이에 필요한 상황정보를 수집하는데 점차 센서의 활용과 응용분야가 확대되고 있다. 상황인식 서비스는 센서로부터 수집된 상황정보의 수집 및 교환을 통해 인식하고, 해석 및 추론 과정을 거쳐 사용자에게 상황에 적절한 서비스를 제공하는 것으로 매장, 의료, 교육 등의 응용분야에서 많이 연구되고 있다. 본 논문에서는 Boole 함수 및 다치 논리함수의 미분을 이용하여 유비쿼터스 환경 하에서 주변상황 등을 인식하는 방법과 그 인식 결과를 해석하고 주변상황의 변화에 따른 적절한 서비스를 제공하는 모델을 제안하고 적용 예를 통하여 확인한다.

• Transactions on Electrical and Electronic Materials
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• v.17 no.6
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• pp.317-328
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• 2016

Over the past few decades, CMOS current comparators have been used in a wide range of applications, including analogue circuits, MVL (multiple-valued logic) circuits, and various electronic products. A current comparator is generally used in an ADC (analog-to-digital) converter of sensors and similar devices, and several techniques and approaches have been implemented to design the current comparator to improve performance. To this end, this paper presents a bibliographical survey of recently-published research on different current comparator topologies for low-power and high-speed applications. Moreover, several aspects of the CMOS current comparator are discussed regarding the design implementation, parameters, and performance comparison in terms of the power dissipation and operational speed. This review will serve as a comparative study and reference for researchers working on CMOS current comparators in low-power and high-speed applications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.1 s.343
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• pp.27-36
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• 2006

Conventional delay-insensitive (DI) data encodings usually require 2N+1 wires for transferring N-bit. To reduce complexity and power dissipation of wires in designing a large scaled chip, an encoder and a decoder circuits, where N-bit data transfer can be peformed with only N+l wires, are proposed. These circuits are based on a quasi delay-insensitive (QDI) model and designed by using current-mode multiple valued logic (CMMVL). The effectiveness of the proposed data transfer mechanism is validated by comparisons with conventional data transfer mechanisms using dual-rail and 1-of-4 encodings through simulation at the 0.25 um CMOS technology. In general, simulation results with wire lengths of 4 mm or larger show that the CMMVL scheme significantly reduces delay-power product ($D{\ast}P$) values of the dual-rail encoding with data rate of 5 MHz or more and the 1-of-4 encoding with data rate of 18 MHz or more. In addition, simulation results using the buffer-inserted dual-rail and 1-of-4 encodings for high performance with the wire length of 10 mm and 32-bit data demonstrate that the proposed CMMVL scheme reduces the D*P values of the dual-rail encoding with data rate of 4 MHz or more and 1-of-4 encoding with data rate of 25 MHz or more by up to $57.7\%\;and\;17.9\%,$ respectively.

• Journal of Communications and Networks
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• v.13 no.5
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• pp.481-493
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• 2011

Multiple-input multiple-output (MIMO) technology provides high data rate and enhanced quality of service for wireless communications. Since the benefits from MIMO result in a heavy computational load in detectors, the design of low-complexity suboptimum receivers is currently an active area of research. Lattice-reduction-aided detection (LRAD) has been shown to be an effective low-complexity method with near-maximum-likelihood performance. In this paper, we advocate the use of systolic array architectures for MIMO receivers, and in particular we exhibit one of them based on LRAD. The "Lenstra-Lenstra-Lov$\acute{a}$sz (LLL) lattice reduction algorithm" and the ensuing linear detections or successive spatial-interference cancellations can be located in the same array, which is considerably hardware-efficient. Since the conventional form of the LLL algorithm is not immediately suitable for parallel processing, two modified LLL algorithms are considered here for the systolic array. LLL algorithm with full-size reduction-LLL is one of the versions more suitable for parallel processing. Another variant is the all-swap lattice-reduction (ASLR) algorithm for complex-valued lattices, which processes all lattice basis vectors simultaneously within one iteration. Our novel systolic array can operate both algorithms with different external logic controls. In order to simplify the systolic array design, we replace the Lov$\acute{a}$sz condition in the definition of LLL-reduced lattice with the looser Siegel condition. Simulation results show that for LR-aided linear detections, the bit-error-rate performance is still maintained with this relaxation. Comparisons between the two algorithms in terms of bit-error-rate performance, and average field-programmable gate array processing time in the systolic array are made, which shows that ASLR is a better choice for a systolic architecture, especially for systems with a large number of antennas.