• Journal of the Korean Society for Aeronautical & Space Sciences
• /
• v.35 no.6
• /
• pp.556-563
• /
• 2007

The current trend of low cost ultra-small satellites is to utilize Commercial Off the Shelf (COTS) parts to save cost, and accordingly, Command and Data Handling (C&DH) that operates the satellite and collects/processes the data is also designed and developed around commercial controllers. However, functionalities of commercial controllers are limited according to the specs outlined by the manufacturer. In order for the commercial controllers to be used for satellites where variety of interfaces is required, a separate interface circuit is required. Therefore, a Multi Digital Data Control System (MDDCS) using Field Programmable Gate Array (FPGA) has been developed in order to expand multiple digital interfaces that are not supported by the commercial controller, and also to compensate for SEU. This has been implemented on Actel A3P1000 using Very High Speed Integrated Circuits Hardware Description Language (VHDL).

• KIISE Transactions on Computing Practices
• /
• v.23 no.2
• /
• pp.104-109
• /
• 2017

We propose a new machine learning algorithm which analyzes daily activity patterns of users from multi-modal wearable sensor data. The proposed model learns and extracts activity patterns using input from wearable devices in real-time. Inspired by cue integration of human's property, we constructed gated multi-modal neural networks which integrate wearable sensor input data selectively by using gate modules. For the experiments, sensory data were collected by using multiple wearable devices in restaurant situations. As an experimental result, we first show that the proposed model performs well in terms of prediction accuracy. Then, the possibility to construct a knowledge schema automatically by analyzing the activation patterns in the middle layer of our proposed model is explained.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.17 no.4
• /
• pp.789-796
• /
• 2013

It is known that the detection of hopping signals without any information about hopping duration and hopping frequency is rather difficult. This paper considers the blind detection of hopping signal's information such as hopping duration and hopping frequency from the sampled wideband signals. In order to find hopping information from the wideband signals, multiple narrow-band filters are required in general, which leads to huge implementation complexity. Instead, this paper employs the polyphase DFT(discrete Fourier transform) filterbank to reduce the implementation complexity. This paper propose hopping signal detection algorithm from the polyphase DFT filterbank output. Specifically, based on the binary image processing, the proposed algorithm is developed to decrease the memory size and H/W complexity. The performance of the proposed algorithm is evaluated through the computer simulation and FPGA (field programmable gate array) implementation.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.20 no.3
• /
• pp.264-272
• /
• 2009

In this paper, a Ka-band 10 W power amplifier module is designed and fabricated using MIC(Microwave Integrated Circuit) module technology which combines multiple power MMIC(Monolithic Microwave Integrated Circuit) chips on a thin film substrate. Modified Wilkinson power dividers/combiners are used for millimeter wave modules and CBFGC-PW-Microstrip transitions are utilized for reducing connection loss and suppressing resonance in the high-gain and high-power modules. The power amplifier module consists of seven MMIC chips and operates in a pulsed mode. for the pulsed mode operation, a gate pulse control circuit supplying the control voltage pulses to MMIC chips is designed and applied. The fabricated power amplifier module shows a power gain of about 58 dB and a saturated output power of 39.6 dBm at a center frequency of the interested frequency band.

• Journal of Electrical Engineering and Technology
• /
• v.9 no.5
• /
• pp.1654-1659
• /
• 2014

Tunneling field-effect transistors (TFETs) are very applicable to low standby-power application by their virtues of low off-current ($I_{off}$) and small subthreshold swing (S). However, low on-current ($I_{on}$) of silicon-based TFETs has been pointed out as a drawback. To improve $I_{on}$ of TFET, a gate-all-around (GAA) TFET based on III-V compound semiconductor with InAs/InGaAs/InP multiple-heterojunction structure is proposed and investigated. Its performances have been evaluated with the gallium (Ga) composition (x) for $In_{1-x}Ga_xAs$ in the channel region. According to the simulation results for $I_{on}$, $I_{off}$, S, and on/off current ratio ($I_{on}/I_{off}$), the device adopting $In_{0.53}Ga_{0.47}As$ channel showed the optimum direct-current (DC) performance, as a result of controlling the Ga fraction. By introducing an n-type InGaAs thin layer near the source end, improved DC characteristics and radio-frequency (RF) performances were obtained due to boosted band-to-band (BTB) tunneling efficiency.

• Journal of IKEEE
• /
• v.27 no.3
• /
• pp.273-279
• /
• 2023

The use of line memory is essential for image filtering in image processing hardware. After input data is stored in line memory, filtering is performed after synchronization to use the stored data. A sync generator is used for synchronization, and in the case of a conventional sync generator, the input sync signal is delayed by one row of the input image. If a signal delayed by two rows is required, it is necessary to connect two modules. This approach increases the size of the hardware and cannot be designed efficiently. In this paper, we propose a sync generator that generates multiple types of delayed signals by adding a finite state machine. The hardware design was coded in Verilog HDL, and performance is verified by applying it to image processing hardware using field programmable gate array board.

• Journal of Korean Society of Occupational and Environmental Hygiene
• /
• v.29 no.4
• /
• pp.464-476
• /
• 2019

Objectives: This study aimed to assess the exposure levels of tollbooth workers to diesel particulate matter using black carbon (BC) and to find the correlations among variables associated with BC using the motor vehicle management act regulated by the Ministry of Land, Infrastructure and Transport. Methods: This study was performed over 14 days at a university in Seoul. BC levels were monitored using an aethalometer and were conducted around the breathing zones of the workers. There were three sampling locations: inside the tollbooth (front gate and rear gate) and an office as a control group. T-test, correlation, and multiple linear regression analysis were performed using SPSS. Results: The geometric mean (GM) of BC_30min concentrations in the exposure group was 2.44 ㎍/㎥, approximately 1.4 times higher than the control group (1.75 ㎍/㎥). The GM of BC_30min concentrations was 2.75 ㎍/㎥ during the heavy traffic time (9-10 am) and 2.30 ㎍/㎥ during non-heavy traffic times (p<0.001). The multiple linear regression analysis shows that the number of all types of vehicles and PM_2.5 concentrations in the atmosphere were factors increasing the GM of BC(ln(BC_30min)) concentrations (adjusted R²=0.42, p<0.001). The workers were constantly exposed to low concentrations (GM of BC_30min=2.44 ㎍/㎥), but they were exposed to peak concentrations instantly (BC_10sec=3545.04 ㎍/㎥). When the GM of BC_30min concentrations was momentarily represented as high, it was identified that a vehicle mainly using diesel fuel or an aging vehicle had passed. Conclusions: A ventilation system should be installed in the closed tollbooth or aging vehicles should be controlled so as not to pass tollbooths.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.20 no.11
• /
• pp.2093-2099
• /
• 2016

This paper describes a design of crypto-processor that supports multiple block cipher algorithms of PRESENT, ARIA, and AES. The crypto-processor integrates three cores that are PRmo (PRESENT with mode of operation), AR_AS (ARIA_AES), and AES-16b. The PRmo core implementing 64-bit block cipher PRESENT supports key length 80-bit and 128-bit, and four modes of operation including ECB, CBC, OFB, and CTR. The AR_AS core supporting key length 128-bit and 256-bit integrates two 128-bit block ciphers ARIA and AES into a single data-path by utilizing resource sharing technique. The AES-16b core supporting key length 128-bit implements AES with a reduced data-path of 16-bit for minimizing hardware. Each crypto-core contains its own on-the-fly key scheduler, and consecutive blocks of plaintext/ciphertext can be processed without reloading key. The crypto-processor was verified by FPGA implementation. The crypto-processor implemented with a $0.18{\mu}m$ CMOS cell library occupies 54,500 gate equivalents (GEs), and it can operate with 55 MHz clock frequency.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.18 no.7
• /
• pp.1657-1662
• /
• 2014

In this paper, the impact of substrate bias($V_{BS}$) on the zero capacitor RAM(Z-RAM) in n-channel junctionless multiple gate MOSFET(MuGFET) has been analyzed experimentally. Junctionless transistors with fin width of 50nm and 1 fin exhibits a memory window of 0.34V and a sensing margin of $1.8{\times}10^4$ at $V_{DS}=3.5V$ and $V_{BS}=0V$. As the positive $V_{BS}$ is applied, the memory window and sensing margin were improved due to an increase of impact ionization. When $V_{BS}$ is increased from 0V to 10V, not only the memory window is increased from 0.34V to 0.96V but also sensing margin is increased slightly. The sensitivity of memory window with different $V_{BS}$ in junctionless transistor was larger than that of inversion-mode transistor. A retention time of junctionless transistor is better than that of inversion-mode transistor due to low Gate Induced Drain Leakage(GIDL) current. To evaluate the device reliability of Z-RAM, the shifts in the Set/Reset voltages and current were measured.

• Journal of The Geomorphological Association of Korea
• /
• v.27 no.1
• /
• pp.1-19
• /
• 2020

A river bed which is submerged in water at high flow and becomes part of the river at low flow, serves as a bridge between the river and the land. The channel bar creates a unique ecosystem with vegetation adapted to the particular environment and the water pool forms a wetland that plays a very important role in the environment. To evaluate anthropogenic impacts on the river bed in the Middle Yeongsangang River, the fluvial landforms in the stream channel were analyzed using multi-temporal remotely-sensed images. In the aerial photograph of 2005 taken before the construction of the large weirs, oxbow lakes, mid-channel bars, point bars, and natural wetlands between the artificial levees were identified. Multiple bars divided the flow of stream water to cause the braided pattern in a particular section. After the construction of the Seungchon weir, aerial photographs of 2013 and 2015 revealed that most of the fluvial landforms disappeared due to the dredging of its riverbed and water level control(maintenance at 7.5El.m). Sentinel-2 images were analyzed to identify differences between before and after the opening of weir gate. Change detection was performed with the near infrared and shortwave infrared spectral bands to effectively distinguish water surfaces from land. As a result, water surface area of the main stream of the Yeongsangang River decreased by 40% from 1.144km² to 0.692km². A large mid-channel bar that has been deposited upstream of the weir was exposed during low water levels, which shows the obvious influence of weir on the river bed. Newly formed unvegetated point bars that were deposited on the inside of a meander bend were identified from the remotely sensed images. As the maintenance period of the weir gate opening was extended, various habitats were created by creating pools and riffles around the channel bars. Considering the ecological and hydrological functions of the river bed, it is expected that the increase in bar areas through weir gate opening will reduce the artificial interference effect of the weir.