• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.3
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• pp.153-159
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• 2009

A CMOS frequency synthesizer for $5{\sim}6$ GHz UNII-band sub-harmonic direct-conversion receiver has been developed. For quadrature down-conversion with sub-harmonic mixing, octa-phase local oscillator (LO) signals are generated by an integer-N type phase-locked loop (PLL) frequency synthesizer. The complex timing issue of feedback divider of the PLL with large division ratio is solved by using multimodulus prescaler. Phase noise of the local oscillator signal is improved by employing the ring-type LC-tank oscillator and switching its tail current source. Implemented in a $0.18{\mu}m$ CMOS technology, the phase noise of the LO signal is lower than -80 dBc/Hz and -113 dBc/Hz at 100 kHz and 1MHz offset, respect-tively. The measured reference spur is lower than -70 dBc and the power consumption is 40 m W from a 1.8 V supply voltage.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.890-893
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• 2003

In this paper, we have designed the fractional-N frequency synthesizer for bluetooth system using 0.35-um CMOS technology and 3.3-V single power supply. The designed synthesizer consist of phase-frequency detector (PFD), charge pump, loop filter, voltage controlled oscillator (VCO), frequency divider, and sigma-delta modulator. A dead zone free PFD is used and a modified charge pump having active cascode transistors is used. A Multi-modulus prescaler having CML D flip-flop is used and VCO having a tuning range from 746 MHz to 2.632 GHz at 3.3 V power supply is used. Total power dissipation is 32 mW and phase noise is -118 dBc/Hz at 1 MHz offset.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.4
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• pp.329-335
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• 2011

In this paper, a dual-band integer-N frequency divider is proposed for 2.4/5.2 GHz multi-standard wireless local area networks. It consists of a multi-modulus imbalance phase switching prescaler and two all-stage programmable counters. It is able to provide dual-band operation with high resolution while maintaining a low power consumption. This frequency divider is integrated with a 5 GHz VCO for multi-standard applications. Measurement results show that the VCO with frequency divider can work at 5.2 GHz with a total power consumption of 22 mW.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1312-1315
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• 2002

This research describes the design of a fully integrated fractional-N frequency synthesizer intended for the local oscillator in IMT-2000 system using 0.18-$\mu\textrm{m}$ CMOS technology and 1.8-V single power supply. The designed fractional-N synthesizer contains following components. Modified charge pump uses active cascode transistors to achieve the high output impedance. A multi-modulus prescaler has modified ECL-like D flip-flop with additional diode-connected transistors for short transient time and high frequency operation. And phase-frequency detector, integrated passive loop filter, LC-tuned VCO having a tuning range from 1.584 to 2.4 ㎓ at 1.8-V power supply, and higher-order sigma-delta modulator are contained. Finally, designed frequency synthesizer provides 5 ㎒ channel spacing with -122.6 dBc/Hz at 1 ㎒ in the WCDMA band and total output power is 28 mW.