• The Transactions of the Korean Institute of Power Electronics
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• v.18 no.1
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• pp.26-36
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• 2013

This paper presents a simple and cost-effective stand-alone rapid battery charging system of 30kW for electric vehicles. The proposed system mainly consists of active front-end rectifier of neutral point clamped 3-level type and non-isolated bi-directional dc-dc converter of multi-phase interleaved half-bridge topology. The charging system is designed to operate for both lithium-polymer and lithium-ion batteries. The complete charging sequence is made up of three sub-interval operating modes; pre-charge mode, constant-current mode, and constant-voltage mode. The pre-charge mode employs the stair-case shaped current profile to accomplish shorter charging time while maintaining the reliable operation of the battery. The proposed system is specified to reach the full-charge state within less than 16min for the battery capacity of 8kWh by supplying the charging current of 78A. Owing to the simple and compact power conversion scheme, the proposed solution has superior module-friendly mechanical structure which is absolutely required to realize flexible power expansion capability in a very high-current rapid charging system.

• Journal of IKEEE
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• v.13 no.1
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• pp.77-86
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• 2009

A wavelet Electrocardiogram(ECG) detector and its analog-to-digital converter(ADC) for low-power implantable cardiac pacemakers are presented in this paper. The proposed wavelet-based ECG detector consists of a wavelet decomposer with wavelet filter banks, a QRS complex detector of hypothesis testing with wavelet-demodulated ECG signals, and a noise detector with zero-crossing points. To achieve high-detection performance with low-power consumption, the multi-scaled product algorithm and soft-threshold algorithm are efficiently exploited. To further reduce the power dissipation, a low-power ADC, which is based on a Successive Approximation Register(SAR) architecture with an on/off-time controlled comparator and passive sample and hold, is also presented. Our algorithmic and architectural level approaches are implemented and fabricated in standard $0.35{\mu}m$ CMOS technology. The testchip shows a good detection accuracy of 99.32% and very low-power consumption of $19.02{\mu}W$ with 3-V supply voltage.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.67 no.1
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• pp.8-15
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• 2018

New methodology for probabilistic reliability based grid expansion planning of HVDC in power system including Wind Turbine Generators(WTG) is developed in this paper. This problem is focused on scenario based optimal selection technique to decide best connection bus of new transmission lines of HVDC in view point of adequacy reliability in power system including WTG. This requires two kinds of modeling and simulation for reliability evaluation. One is how is reliability evaluation model and simulation of WTG. Another is to develop a failure model of HVDC. First, reliability evaluation of power system including WTG needs multi-state simulation methodology because of intermittent characteristics of wind speed and nonlinear generation curve of WTG. Reliability methodology of power system including WTG has already been developed with considering multi-state simulation over the years in the world. The multi-state model already developed by authors is used for WTG reliability simulation in this study. Second, the power system including HVDC includes AC/DC converter and DC/AC inverter substation. The substation is composed of a lot of thyristor devices, in which devices have possibility of failure occurrence in potential. Failure model of AC/DC converter and DC/AC inverter substation in order to simulate HVDC reliability is newly proposed in this paper. Furthermore, this problem should be formulated in hierarchical level II(HLII) reliability evaluation because of best bus choice problem for connecting new HVDC and transmission lines consideration. HLII reliability simulation technique is not simple but difficult and complex. CmRel program, which is adequacy reliability evaluation program developed by authors, is extended and developed for this study. Using proposed method, new HVDC connected bus point is able to be decided at best reliability level successfully. Methodology proposed in this paper is applied to small sized model power system.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.5
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• pp.57-66
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• 1999

This paper describes a 12b, 50 Msample/s CMOS AID converter using an acquisition-time minimization technique for the high-speed sampling rate of 50 MHz level. The proposed ADC is implemented in a $0.35\mu\textrm{m}$ double-poly five-metal n-well CMOS technology and adopts a typical multi-step pipelined architecture to optimize sampling rate, resolution, and chip area. The speed limitation of conventional pipelined ADCs comes from the finite bandwidth and resulting speed of residue amplifiers. The proposed acquisition-time minimization technique reduces the acquisition time of residue amplifiers and makes the waveform of amplifier outputs smooth by controlling the operating current of residue amplifiers. The simulated power consumption of the proposed ADC is 197 mW at 3 V with a 50 MHz sampling rate. The chip size including pads is $3.2mm\times3.6mm$.

• Journal of Ocean Engineering and Technology
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• v.27 no.1
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• pp.85-92
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• 2013

This paper deals with the resonant type of a WEC (wave energy converter) and the determination method of its geometric parameters which were obtained to construct the robust and optimal structure, respectively. In detail, the optimization problem is formulated with the constraints composed of the response surfaces which stand for the resonance period(heave, pitch) and the meta center height of the buoy. Use of a signal-to-noise ratio calculated from normalized multi-objective results with the weight factor can help to select the robust design level. In order to get the sample data set, the motion responses of the power buoy were analyzed using the BEM (boundary element method)-based commercial code. Also, the optimization result is compared with a robust design for a feasibility study. Finally, the power efficiency of the WEC with the optimum design variables is estimated as the captured wave ratio resulting from absorbed power which mainly related to PTO (power take off) damping. It could be said that the resultant of the WEC design is the economical optimal design which satisfy the given constraints.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.23 no.5
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• pp.88-95
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• 2009

This paper is the research on the development of power conversion system for the fuel cell. In composing the DC/DC converters which have high boost voltage ratio, unlike the conventional method a new multi DC/DC converter system is proposed that the diode and the condenser and the reactor can be reduced by connecting the secondary side output of the transformer. In this system the rectifier part and the filter part of the secondary side in the power transformer that is connecting in series are composed into a single module, which is the strong advantage and the number of level can be easily increased. A new variable shift phase switching method is also suggested that it makes possible to reduce the output voltage ripples in the proposed system. All the factors mentioned above have been verified through simulations and experiments, and the proposed converter is considered very useful in the demanded load which requires a wide of the output.

• Journal of Power Electronics
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• v.19 no.4
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• pp.922-933
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• 2019

The arm inductance (AI) of a modular multilevel converter (MMC) affects both the fault and circulating current magnitudes. In addition, it has an impact on the inverter efficiency and harmonic content. In this study, the AI of a three-phase MMC is optimized in a novel way in terms of DC voltage utilization, harmonics and efficiency. This MMC has 10 submodules (SM) per arm and the power circuit topology of the SM is a half-bridge. The optimum AI is adopted and verified in an MMC that has 100 SMs per arm. Then the phase shift (PS) and phase disposition (PD) pulse width modulation (PWM) methods are investigated for better DC voltage utilization, efficiency and harmonics. It is found that similar performances are obtained for both modulation techniques in terms of DC voltage utilization. However, the total harmonic distortion (THD) of the PS-PWM is found to be 0.02%, which is slightly lower than the THD of the PD-PWM at 0.16%. In efficiency calculations, the switching and conduction losses for all of the semiconductor are considered separately and the minimum efficiency of the 100-SM based MMC is found to be 99.62% for the PS-PWM and 99.64% for the PD-PWM with the optimal value of the AI. Simulation results are verified with an experimental prototype of a 6-SM based MMC.

• Proceedings of the KIPE Conference
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• 2001.12a
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• pp.139-143
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• 2001

Recently, the interest on power quality has been hot issue. The equipments cause voltage disturbance and has become more sensitive to the voltage disturbance. This paper deals with 5-Level H-Bridge Line-Inter active Dynamic Voltage Restorer(LIDVR) system. The LIDVR has following advantages in comparison with the DVR with series injection transformer It has the power factor near to unity under normal source voltage, can compensate the harmonic current of the load and the instant interruption, and has the fast response. First, the construction, the operation mode and algebraic modeling of LIDVR are reviewed. And then a voltage controller is proposed to get sinusoidal load voltage with constant amplitude. To find PWM method suitable for H-Bridge converter, two PWM methods are compared and analyzed. Finally, simulation results verify the proposed 5-level H-Bridge LIDVR system.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.63 no.8
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• pp.1046-1054
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• 2014

In this paper, a hardware prototype for the 10kVA 11-level MMC was built and various experimental works were conducted to verify the operation algorithms of MMC. The hardware prototype was designed using computer simulation with PSCAD/EMTDC software. After manufactured in the lab, the hardware prototype was tested to verify the modulation algorithms to form the output voltage, the balancing algorithm to equalize the sub-module capacitor voltage, and the redundancy operation algorithm to improve the system reliability. The developed hardware prototype can be utilized for analyzing the basic operation and performance improvement of MMC according to the modulation and redundancy operation scheme. It also can be utilize to analyze the basic operational characteristics of HVDC system based on MMC.

• Journal of Power Electronics
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• v.16 no.2
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• pp.464-472
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• 2016

This study applies the selective harmonic elimination (SHE) technique to design and operate a regulated AC/DC/AC power supply suitable for maritime military applications and underground trains. The input is a single 50/60 Hz AC voltage, and the output is a 400 Hz regulated voltage. The switching angles for a multi-level inverter and transformer turns ratio are determined to operate with special connected transformers with equal power ratings and produce an almost sinusoidal current. As a result of its capability of directly controlling harmonics, the SHE technique is applicable to apparatus with congenital immunity to specific harmonics, such as series-connected transformers, which are specially designed to equally share the total load power. In the present work, a single-phase 50/60 Hz input source is rectified via a semi-controlled bridge rectifier to control DC voltage levels and thereby regulate the output load voltage at a constant level. The DC-rectified voltage then supplies six single-phase quazi-square H-bridge inverters, each of which supplies the primary of a single-phase transformer. The secondaries of the six transformers are connected in series. Through off-line calculation, the switching angles of the six inverters and the turns ratios of the six transformers are designed to ensure equal power distribution for the transformers. The SHE technique is also employed to eliminate the higher-order harmonics of the output voltage. A digital implementation is carried out to determine the switching angles. Theoretical results are demonstrated, and a scaled-down experimental 600 VA prototype is built to verify the validity of the proposed system.