• 전력전자학회논문지
• /
• 제18권1호
• /
• pp.26-36
• /
• 2013

This paper presents a simple and cost-effective stand-alone rapid battery charging system of 30kW for electric vehicles. The proposed system mainly consists of active front-end rectifier of neutral point clamped 3-level type and non-isolated bi-directional dc-dc converter of multi-phase interleaved half-bridge topology. The charging system is designed to operate for both lithium-polymer and lithium-ion batteries. The complete charging sequence is made up of three sub-interval operating modes; pre-charge mode, constant-current mode, and constant-voltage mode. The pre-charge mode employs the stair-case shaped current profile to accomplish shorter charging time while maintaining the reliable operation of the battery. The proposed system is specified to reach the full-charge state within less than 16min for the battery capacity of 8kWh by supplying the charging current of 78A. Owing to the simple and compact power conversion scheme, the proposed solution has superior module-friendly mechanical structure which is absolutely required to realize flexible power expansion capability in a very high-current rapid charging system.

• 전기전자학회논문지
• /
• 제13권1호
• /
• pp.77-86
• /
• 2009

본 논문에서 이식형 심장 박동 조율기를 위한 심전도 검출기와 아날로그-디지털 변환기(ADC)를 설계한다. 제안한 웨이블렛 심전도 검출기는 웨이블렛 필터 뱅크 구조의 웨이블렛 변조기, 웨이블렛 합성된 심전도 신호의 가설 검정을 통한 QRS 신호 검출기와 0-교차점을 이용한 잡음 검출기로 구성된다. 저전력 소모의 동작을 유지하며 보다 높은 검출 정확도를 갖는 심전도 검출기의 구현을 위해, 다중스케일 곱의 알고리즘과 적응형의 임계값을 갖는 알고리즘을 사용하였다. 또한 심전도 검출기의 입력단에 위치하는 저전력 Successive Approximation Register ADC의 구현을 위해, 신호 변환의 주기 중, 매우 짧은 시간 동안에만 동작하는 비교기와 수동 소자로 구성되는 Sample&Hold를 사용하였다. 제안한 회로는 표준 CMOS $0.35{\mu}m$ 공정을 사용하여 집적 및 제작되었고, 99.32%의 높은 검출 정확도와 3V의 전원 전압에서 $19.02{\mu}W$의 매우 낮은 전력 소모를 갖는 것을 실험을 통해 확인하였다.

• 전기학회논문지
• /
• 제67권1호
• /
• pp.8-15
• /
• 2018

New methodology for probabilistic reliability based grid expansion planning of HVDC in power system including Wind Turbine Generators(WTG) is developed in this paper. This problem is focused on scenario based optimal selection technique to decide best connection bus of new transmission lines of HVDC in view point of adequacy reliability in power system including WTG. This requires two kinds of modeling and simulation for reliability evaluation. One is how is reliability evaluation model and simulation of WTG. Another is to develop a failure model of HVDC. First, reliability evaluation of power system including WTG needs multi-state simulation methodology because of intermittent characteristics of wind speed and nonlinear generation curve of WTG. Reliability methodology of power system including WTG has already been developed with considering multi-state simulation over the years in the world. The multi-state model already developed by authors is used for WTG reliability simulation in this study. Second, the power system including HVDC includes AC/DC converter and DC/AC inverter substation. The substation is composed of a lot of thyristor devices, in which devices have possibility of failure occurrence in potential. Failure model of AC/DC converter and DC/AC inverter substation in order to simulate HVDC reliability is newly proposed in this paper. Furthermore, this problem should be formulated in hierarchical level II(HLII) reliability evaluation because of best bus choice problem for connecting new HVDC and transmission lines consideration. HLII reliability simulation technique is not simple but difficult and complex. CmRel program, which is adequacy reliability evaluation program developed by authors, is extended and developed for this study. Using proposed method, new HVDC connected bus point is able to be decided at best reliability level successfully. Methodology proposed in this paper is applied to small sized model power system.

• 전자공학회논문지C
• /
• 제36C권5호
• /
• pp.57-66
• /
• 1999

본 논문에서는 50 MHz 수준의 고속 신호 샘플링을 위해 정착시간 최소화 기법을 적용한 12 비트 50 MHz CMOS A/D 변환기(analon-to-digital-converter : ADC) 회로를 제안한다. 제안하는 ADC는 0.35㎛ double-poly five-metal n-well CMOS 공정을 사용하여 설계 및 레이아웃되었으며, 응용되는 시스템의 속도, 해상도 및 면적 등의 사양을 고려하여 다단 파이프라인 구조가 적용되었다. 기존의 파이프라인 구조를 가진 ADC의 경우, 동작속도를 제한하는 결정적인 회로 불럭은 잔류전압 증폭기이나, 제안하는 정착 시간 최소화 기법은 이러한 잔류전압 증폭기의 동작 전류 제어를 통해 정착시간 단축 및 출력신호의 불규칙성을 최소한으로 줄인다. 3 V 전원전압에서 50 MHz 클럭 주파수를 사용하여 모의실험한 결과, 입출력단을 포함한 전체 ADC는 197mW의 전력소모를 나타내었고, 입출력단의 패드를 포함한 전체 칩면적은 3.2mm×3.6mm이다.

• 한국해양공학회지
• /
• 제27권1호
• /
• pp.85-92
• /
• 2013

This paper deals with the resonant type of a WEC (wave energy converter) and the determination method of its geometric parameters which were obtained to construct the robust and optimal structure, respectively. In detail, the optimization problem is formulated with the constraints composed of the response surfaces which stand for the resonance period(heave, pitch) and the meta center height of the buoy. Use of a signal-to-noise ratio calculated from normalized multi-objective results with the weight factor can help to select the robust design level. In order to get the sample data set, the motion responses of the power buoy were analyzed using the BEM (boundary element method)-based commercial code. Also, the optimization result is compared with a robust design for a feasibility study. Finally, the power efficiency of the WEC with the optimum design variables is estimated as the captured wave ratio resulting from absorbed power which mainly related to PTO (power take off) damping. It could be said that the resultant of the WEC design is the economical optimal design which satisfy the given constraints.

• 조명전기설비학회논문지
• /
• 제23권5호
• /
• pp.88-95
• /
• 2009

본 논문은 연료전지용 전력변환기 개발에 관한 연구로 높은 승압비를 갖는 DC/DC 컨버터를 구성함에 있어서 기존 방식과 달리 변압기의 2차측 출력을 직렬로 연결하여 다이오드와 콘덴서 및 리액터를 줄일 수 있는 구조의 새로운 멀티 DC/DC 컨버터의 구조를 제안한다. 이러한 구조는 직렬 연결된 변압기의 2차측의 정류부분과 필터부분이 하나의 모듈로 구성되는 장점을 가지며 레벨수의 증가가 용이하다. 또한 제안된 구조에서 출력전압 리플을 줄일 수 있는 새로운 가변 위상 변위형 스위칭 방식을 제안한다. 이러한 모든 사항을 시뮬레이션과 실험을 통하여 검증 하였으며, 제안된 컨버터는 넓은 영역의 출력이 요구되는 부하에 매우 유용할 것으로 사료된다.

• Journal of Power Electronics
• /
• 제19권4호
• /
• pp.922-933
• /
• 2019

The arm inductance (AI) of a modular multilevel converter (MMC) affects both the fault and circulating current magnitudes. In addition, it has an impact on the inverter efficiency and harmonic content. In this study, the AI of a three-phase MMC is optimized in a novel way in terms of DC voltage utilization, harmonics and efficiency. This MMC has 10 submodules (SM) per arm and the power circuit topology of the SM is a half-bridge. The optimum AI is adopted and verified in an MMC that has 100 SMs per arm. Then the phase shift (PS) and phase disposition (PD) pulse width modulation (PWM) methods are investigated for better DC voltage utilization, efficiency and harmonics. It is found that similar performances are obtained for both modulation techniques in terms of DC voltage utilization. However, the total harmonic distortion (THD) of the PS-PWM is found to be 0.02%, which is slightly lower than the THD of the PD-PWM at 0.16%. In efficiency calculations, the switching and conduction losses for all of the semiconductor are considered separately and the minimum efficiency of the 100-SM based MMC is found to be 99.62% for the PS-PWM and 99.64% for the PD-PWM with the optimal value of the AI. Simulation results are verified with an experimental prototype of a 6-SM based MMC.

• 전력전자학회:학술대회논문집
• /
• 전력전자학회 2001년도 추계학술대회 논문집
• /
• pp.139-143
• /
• 2001

Recently, the interest on power quality has been hot issue. The equipments cause voltage disturbance and has become more sensitive to the voltage disturbance. This paper deals with 5-Level H-Bridge Line-Inter active Dynamic Voltage Restorer(LIDVR) system. The LIDVR has following advantages in comparison with the DVR with series injection transformer It has the power factor near to unity under normal source voltage, can compensate the harmonic current of the load and the instant interruption, and has the fast response. First, the construction, the operation mode and algebraic modeling of LIDVR are reviewed. And then a voltage controller is proposed to get sinusoidal load voltage with constant amplitude. To find PWM method suitable for H-Bridge converter, two PWM methods are compared and analyzed. Finally, simulation results verify the proposed 5-level H-Bridge LIDVR system.

• 전기학회논문지
• /
• 제63권8호
• /
• pp.1046-1054
• /
• 2014

In this paper, a hardware prototype for the 10kVA 11-level MMC was built and various experimental works were conducted to verify the operation algorithms of MMC. The hardware prototype was designed using computer simulation with PSCAD/EMTDC software. After manufactured in the lab, the hardware prototype was tested to verify the modulation algorithms to form the output voltage, the balancing algorithm to equalize the sub-module capacitor voltage, and the redundancy operation algorithm to improve the system reliability. The developed hardware prototype can be utilized for analyzing the basic operation and performance improvement of MMC according to the modulation and redundancy operation scheme. It also can be utilize to analyze the basic operational characteristics of HVDC system based on MMC.

• Journal of Power Electronics
• /
• 제16권2호
• /
• pp.464-472
• /
• 2016

This study applies the selective harmonic elimination (SHE) technique to design and operate a regulated AC/DC/AC power supply suitable for maritime military applications and underground trains. The input is a single 50/60 Hz AC voltage, and the output is a 400 Hz regulated voltage. The switching angles for a multi-level inverter and transformer turns ratio are determined to operate with special connected transformers with equal power ratings and produce an almost sinusoidal current. As a result of its capability of directly controlling harmonics, the SHE technique is applicable to apparatus with congenital immunity to specific harmonics, such as series-connected transformers, which are specially designed to equally share the total load power. In the present work, a single-phase 50/60 Hz input source is rectified via a semi-controlled bridge rectifier to control DC voltage levels and thereby regulate the output load voltage at a constant level. The DC-rectified voltage then supplies six single-phase quazi-square H-bridge inverters, each of which supplies the primary of a single-phase transformer. The secondaries of the six transformers are connected in series. Through off-line calculation, the switching angles of the six inverters and the turns ratios of the six transformers are designed to ensure equal power distribution for the transformers. The SHE technique is also employed to eliminate the higher-order harmonics of the output voltage. A digital implementation is carried out to determine the switching angles. Theoretical results are demonstrated, and a scaled-down experimental 600 VA prototype is built to verify the validity of the proposed system.