• Journal of Korea Multimedia Society
• /
• v.13 no.8
• /
• pp.1163-1170
• /
• 2010

In this paper, in order to develop a remote progress management system through the Internet, we show a design method to make easy maintenance by developing the system with both the JAVA language and GoF Design Patterns. For the system implementation, we added the RS232C and RS422/RS485 communication modules to PLC(Programmable Logic Controller) in the control box which provide the real time status data of machines. Also we set up the RS232C to Ethernet converter based on wireless environment to communicate the PLC control data. We use JAVA Swing components to implement the multi-tier architecture system supported the GUI of the Applet and Frame at the same time so that the manager grasps the progress of work easily at the remote machines through the Internet. The key objective of the multi-tier architecture is to share resources among clients, this proposed system can help to develop the software to control the remote machine, and also it has the advantage that developer who wants to make a similar software can make easy to add new function reusing the existing codes.

• Journal of the Korea Convergence Society
• /
• v.8 no.10
• /
• pp.209-214
• /
• 2017

The aim of the present study was to analyze the factors that affects the peer attachment in Korean youth. Subjects were 419 middle school students (210 male, 209 female). Dependent variable was defined as peer attachment. Explanatory variables were included as gender, academic achievement satisfaction, subjective household economy level, parent - child dialogue frequency, subjective health status, depression symptom, self - esteem, subjective life satisfaction, and mobile phone dependency. In the multi-layer perceptron artificial neural network algorithm analysis, depression symptoms, gender, parent-child dialogue level for school life, subjective household economy level, subjective health status were significantly associated with peer attachment in Korean youth. Based on this result, systematic programs are required in order to prevention of peer attachment in Korean youth.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.10 no.2
• /
• pp.97-102
• /
• 2010

In this paper, an area-efficient FFT processor is proposed for IEEE 802.16e mobile WiMax systems. The proposed scalable FFT processor can support the variable length of 128, 512, 1024 and 2048. By reducing the required number of non-trivial multipliers with mixed-radix (MR) and multi-path delay commutator (MDC) architecture, the complexity of the proposed FFT processor is dramatically decreased without sacrificing system throughput. The proposed FFT processor was designed in hardware description language (HDL) and synthesized to gate-level circuits using 0.18um CMOS standard cell library. With the proposed architecture, the gate count for the processor is 46K and the size of memory is 64Kbits, which are reduced by 16% and 27%, respectively, compared with those of the 4-channel radix-2 MDC (R2MDC) FFT processor.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.12
• /
• pp.87-95
• /
• 2009

In this paper, an area-efficient FFT processor is proposed for MIMO-OFDM based SDR systems. The proposed scalable FFT processor can support the variable length of 64, 128, 512, 1024 and 2048. By reducing the required number of non-trivial multipliers with mixed-radix (MR) and multi-path delay commutator (MDC) architecture, the complexity of the proposed FFT processor is dramatically decreased without sacrificing system throughput The proposed FFT processor was designed in hardware description language (HDL) and synthesized to gate4eve1 circuits using 0.18um CMOS standard cell library. With the proposed architecture, the gate count for the processor is 46K and the size of memory is 64Kbits, which are reduced by 59% and 39%, respectively, compared with those of the 4-channel radix-2 single-path delay feedback (R2SDF) FFT processor. Also, compared with 4-channel radix-2 MDC (R2MDC) FFT processor, it is confirmed that the gate count and memory size are reduced by 16.4% and 26.8, respectively.

• Journal of the Korea Convergence Society
• /
• v.9 no.10
• /
• pp.45-53
• /
• 2018

Recently, studies about bilingual word embedding have been gaining much attention. However, bilingual word embedding with Korean is not actively pursued due to the difficulty in obtaining a sizable, high quality corpus. Local embeddings that can be applied to specific domains are relatively rare. Additionally, multi-word vocabulary is problematic due to the lack of one-to-one word-level correspondence in translation pairs. In this paper, we crawl 868,163 paragraphs from a Korean-English law corpus and propose three mapping strategies for word embedding. These strategies address the aforementioned issues including multi-word translation and improve translation pair quality on paragraph-aligned data. We demonstrate a twofold increase in translation pair quality compared to the global bilingual word embedding baseline.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.3
• /
• pp.41-50
• /
• 2010

In this paper, an area-efficient symbol detector is proposed for MIMO communication systems with two transmit and two receive antennas. The proposed symbol detector can support both the spatial multiplexing mode and spatial diversity mode for MIMO transmission technique, and shows the optimal maximum likelihood (ML) performance. Also, by sharing the hardware block with multi-stage pipeline structure and using the complex multiplier based on polar-coordinate，the complexity of the proposed architecture is dramatically decreased. The proposed symbol detector was designed in hardware description language (HDL) and implemented with Xilinx Virtex-5 FPGA. With the proposed architecture, the number of logic slices for the proposed symbol detection is 52490 and the number of DSP48s (dedicated multiplier) is 52, which are reduced by 35.3% and 85.3%, respectively, compared with the conventional architecture.

• KEPCO Journal on Electric Power and Energy
• /
• v.3 no.2
• /
• pp.89-97
• /
• 2017

The substation is a critical node in the power network where power is transformed in the power generation, transmission and distribution system. The IEC 61850 is a global standard which proposes efficient substation automation by defining interoperable communication and data modelling techniques. In order to achieve this level of interoperability and automation, the IEC 61850 (Part 6) defines System Configuration description Language (SCL). The SCL is an XML based file format for defining the abstract model of primary and secondary substation equipment, communications systems and also the relationship between them. It enables the interoperable exchange of data during substation engineering by standardizing the description of applications at different stages of the engineering process. To achieve the seamless interoperability, multi-vendor devices are required to adhere completely to the IEC 61850. This paper proposes an efficient algorithm required for verifying the interoperability of multi-vendor devices by checking the adherence of the SCL file to specifications of the standard. Our proposed SCL validation algorithm consists of schema validation and other functionalities including information model validation using UML data model, the Vendor Defined Extension model validation, the User Defined Rule validation and the IED Engineering Table (IET) consistency validation. It also integrates the standard UCAIUG (Utility Communication Architecture International Users Group) Procedure validation for quality assurance testing. Our proposed algorithm is not only flexible and efficient in terms of ensuring interoperable functionality of tested devices, it is also convenient for use by system integrators and test engineers.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.11 no.4
• /
• pp.319-324
• /
• 2018

In this paper, we designed and implemented a code conversion method between ISO/IEC 10646 and the multi-byte code set. The Universal Multiple-Octet Coded Character Set(UCS) provides codes for more than 65,000 characters, huge increase over ASCII's code capacity of 128 characters. It is applicable to the representation, transmission, interchange, processing, storage, input and presentation of the written form of the language throughout the world. Therefore, it is so important to guide on code conversion methods to their customers during customer systems are migrated to the environment which the UCS code system is used and/or the current code systems, i.e., ASCII PC code and EBCDIC host code, are used with the UCS together. Code conversion utility including the mapping table between the UCS and IBM new host code is shown for the purpose of the explanation of code conversion algorithm and its implementation in the system. The programs are successfully executed in the real system environments and so can be delivered to the customer during its migration stage from the UCS to the current IBM code system and vice versa.

• Journal of the Semiconductor & Display Technology
• /
• v.10 no.4
• /
• pp.7-13
• /
• 2011

In this paper, the IC(Integrated Circuit) for multi-channel synchronous communication was designed by using FPGA and VHDL language. The existing chips for synchronous communication that has been used commercially are composed for one to two channels. Therefore, when communication system with three channels or more is made, the cost becomes high and it becomes complicated for communication system to be realized and also has very little buffer, load that is placed into Microprocessor increases heavily in case of high speed communication or transmission of high-capacity data. The designed IC was improved the function and performance of communication system and reduced costs by designing 8 synchronous communication channels with only one IC, and it has the size of transmitter/receiver buffer with 1024 bytes respectively and consequently high speed communication became possible. It was designed with a communication signal of a form various encoding. To detect errors of communications, the CRC-ITU-T logic and channel MUX logic was designed with hardware logics so that the malfunction can be prevented and errors can be detected more easily and input/output port regarding each communication channel can be used flexibly and consequently the reliability of system was improved. In order to show the performance of designed IC, the test was conducted successfully in Quartus simulation and experiment and the excellence was compared with the 85C3016VSC of ZILOG company that are used widely as chips for synchronous communication.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.47 no.4
• /
• pp.15-20
• /
• 2010

The three dimensional information is extracted and visualized using by stereo images of the object and the method for a 3D stereoscopic image is presented by the vergence control algorithm. The matching, which is applied a undistortion of lens and the energy function, is executed for the efficient extraction three dimensional information. Especially, applying the optimized method of matched line to the multi direction of the disparity imges. The disadvantages of multi directional method and reliability expansion method is collected. The matched interesting range of the three dimensional information is visualized using by VRML and more 3D stereoscopic image is visualized through the vergence control according to distance of the object. more improved three dimensional information is provided to observer by visualizing both of them at the same time.