• Proceedings of the Korean Society of Precision Engineering Conference
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• 2010.05a
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• pp.653-654
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• 2010

• Journal of the Microelectronics and Packaging Society
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• v.19 no.4
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• pp.45-50
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• 2012

A family of multi-die DRAM packages was developed that incorporate the full functionality of an SODIMM into a single package. Using a common ball assignment analogous to the edge connector of an SODIMM, a broad range of memory types and assembly structures are supported in this new package. In particular DDR3U, LPDDR3 and DDR4RS are all supported. The center-bonded DRAM use face-down wirebond assembly, while the peripherybonded LPDDR3 use the face-up configuration. Flip chip assembly as well as TSV stacked memory is also supported in this new technology. For the center-bonded devices (DDR3, DDR4 and LPDDR3 ${\times}16$ die) and for the face up wirebonded ${\times}32$ LPDDR3 devices, a simple manufacturing flow is used: all die are placed on the strip in a single machine insertion and are sourced from a single wafer. Wirebonding is also a single insertion operation: all die on a strip are wirebonded at the same time. Because the locations of the power signals is unchanged for these different types of memories, a single consolidated set of test hardware can be used for testing and burn-in for all three memory types.

• Journal of the Semiconductor & Display Technology
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• v.6 no.1 s.18
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• pp.17-22
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• 2007

Recent new packages such as MCP(Multi-Chip Package), QDP(Quadratic Die Package) and DDP(Dual Die Package) have stack type configuration. This kind of multi-layer package is thicker than single layer package. So there is need for the low height looping technology in wirebonder to make these packages thinner. There is stiff zone above ball in wirebonder wire which is called HAZ(Heat Affect Zone). When making low height loop (below $80\;{\mu}m$) with traditional forward loop, stiff wire in HAZ(Heat Affected Zone) above ball is bended and weakened. So the traditional forward looping method cannot be applied to low height loop. SSB(stand-off stitch) wire bonding method was applied to many packages which require very low loops. The drawback of SSB method is making frequent errors at making ball, neck damage above ball on lead and the weakness of ball bonding on lead. The alternative looping method is BNL(ball neckless) looping technology which is already applied to some package(DDP, QDP). The advantage of this method is faster in bonding process and making little errors in wire bonding compared with SSB method. This paper presents the result of BNL looping technology applied in assembly house and several issues related to low loop height consistence and BNL zone weakness.

• International Journal of Precision Engineering and Manufacturing
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• v.7 no.1
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• pp.3-8
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• 2006

This paper deals with an automated computer-aided process planning and die design system by which designer can determine operation sequences even if they have a little experience in process planning and die design for axisymmetric products. An attempt is made to link programs incorporating a number of expert design rules with the process variables obtained by commercial FEM softwares, DEFORM and ANSYS, to form a useful package. The system can provide a flexible process based on either the reduction in the number of forming sequences by combining the possible two processes in sequence, or the reduction of deviation of the distribution on the level of the required forming loads by controlling the forming ratios. Especially in die design module optimal design technique and horizontal split of die insert were investigated for determining appropriate dimensions of components of multi-former die set. Results obtained, using the modules, enable the design and manufacture of a die set for a multi-former to be more efficiently performed.

• Journal of the Korean Society for Precision Engineering
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• v.16 no.3 s.96
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• pp.25-29
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• 1999

The lead frame manufactured by press stamping process, is an important part of semiconductor. The recent technical trend of semiconductor, chip sized and high performance package technology, requires the lead frame to be of more multi-leads and of fine ILP (Inner Lead Pitch). As the ILP is getting finer, its corresponding punch of the stamping die is getting narrower. The punch narrower than its stamping limit has been broken due to local buckling. This paper analyzed the phenomena of punch breakdown. Moreover, the punch design was modified to increase the critical limit of buckling force. This paper, also, suggested new design rules of the punch, which asks the modification of its lead frame design that has to be considered in the stage of semiconductor package design. The new design rules of lead frame design yields a good reliability of semiconductor package as well as a good quality of lead frame.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.10a
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• pp.1307-1311
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• 2004

This paper deals with an automated computer-aided process planning and die design system by which designer can determine operation sequences even if they have a little experience in process planning and die design for axisymmetric products. An attempt is made to link programs incorporating a number of expert design rules with the process variables obtained by commercial FEM softwares, DEFORM and ANSYS, to form a useful package. They can provide a flexible process based on either the reduction in the number of forming sequences by combining the possible two processes in sequence, or the reduction of deviation of the distribution on the level of the required forming loads by controlling the forming ratios. Especially in die design module an optimal design technique and horizontal split die were investigated for determining appropriate dimensions of components of multi-former die set. It is constructed that the proposed method can be beneficial for improving the tool life of die set at practice.

• Journal of the Korean Society for Precision Engineering
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• v.21 no.9
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• pp.32-40
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• 2004

This paper deals with an automated computer-aided process planning and die design system by which designer can determine operation sequences even if they have a little experience in process planning and die design for axisymmetric products. An attempt is made to link programs incorporating a number of expert design rules with the process variables obtained by commercial FEM softwares, DEFORM and ANSYS, to form a useful package. The system is composed of four main modules. The process planning and the die design modules consider several factors, such as the complexities of preform geometry, punch and die profiles, specifications of available multi former, and the availability of standard parts. They can provide a flexible process based on either the reduction in the number of forming sequences by combining the possible two processes in sequence, or the reduction of deviation of the distribution on the level of the required forming loads by controlling the forming ratios. Especially in die design module an optimal design technique and horizontal split die were investigated for determining appropriate dimensions of components of multi-former die set. It is constructed that the proposed method can be beneficial for improving the tool life of die set at practice.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.2
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• pp.7-15
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• 2012

Semiconductor packages are increasingly moving toward miniaturization, lighter and multi-functions for mobile application, which requires highly integrated multi-stack package. To meet the industrial demand, the package and silicon chip become thinner, and ultra-thin packages will show serious reliability problems such as warpage, crack and other failures. These problems are mainly caused by the mismatch of various package materials and geometric dimensions. In this study we perform the numerical analysis of the warpage deformation and thermal stress of 4-layer stacked FBGA package after EMC molding and reflow process, respectively. After EMC molding and reflow process, the package exhibits the different warpage characteristics due to the temperature-dependent material properties. Key material properties which affect the warpage of package are investigated such as the elastic moduli and CTEs of EMC and PCB. It is found that CTE of EMC material is the dominant factor which controls the warpage. The results of RSM optimization of the material properties demonstrate that warpage can be reduced by $28{\mu}m$. As the silicon die becomes thinner, the maximum stress of each die is increased. In particular, the stress of the top die is substantially increased at the outer edge of the die. This stress concentration will lead to the failure of the package. Therefore, proper selection of package material and structural design are essential for the ultra-thin die packages.

• Journal of the Korean Society for Precision Engineering
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• v.20 no.4
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• pp.29-38
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• 2003

This paper deals with an automated computer-aided process planning and die design system with which designer can determine operation sequences even after only a little experience in process planning and die design of multi former-bolt products by multi-stage former working. The approach is based on knowledge-based rules, and a process knowledge base consisting of design rules is built. Knowledge fur the system is formulated from plasticity theories, empirical results and the empirical knowledge of field experts. Programs for the system have been written in AutoLISP for AutoCAD with a personal computer. An attempt is made to link programs incorporating a number of expert design rules with the process variables obtained by commercial FEM softwares, DEFORM and ANSYS, to form a useful package. The system is composed of four main modules. The process planning and die design module considers several factors, such as the complexities of preform geometry, punch and die profiles, specifications of available multi former, and the availability of standard parts. It can provide a flexible process based on either the reduction in the number of forming sequences by combining the possible two processes in sequence, or the reduction of deviation of the distribution and the level of the required forming loads by controlling the forming ratios. The system uses 2D geometry recognition and is integrated with the technology of process planning, die design, and CAE analysis. The standardization of die parts for multi former-bolt products requiring a cold forging process is described. The system developed makes it possible to design and manufacture multi former-bolt products more efficiently.

• Journal of the Korean Society for Precision Engineering
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• v.20 no.10
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• pp.183-190
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• 2003

Major device failures such as die cracking, interfacial delamination and warpage in flip chip packages are due to excessive heat and thermal gradients- There have been significant researches toward understanding the thermal performance of electronic packages, but the majority of these studies do not take into account the combined effects of thermo-mechanical interactions of the different package constituents. This paper investigates the thermo-mechanical performance of flip chip package constituents based on the finite element method with thermo-mechanically coupled elements. Delaminations with different lengths between the silicon die and underfill resin interfaces were introduced to simulate the defects induced during the assembly processes. The temperature gradient fields and the corresponding stress distributions were analyzed and the results were compared with isothermal case. Parametric studies have been conducted with varying thermal conductivities of the package components, substrate board configurations. Compared with the uniform temperature distribution model, the model considering the temperature gradients provided more accurate stress profiles in the solder interconnections and underfill fillet. The packages with prescribed delaminations resulted in significant changes in stress in the solder. From the parametric study, the coefficients of thermal expansion and the package configurations played significant roles in determining the stress level over the entire package, although they showed little influence on stresses profile within the individual components. These observations have been implemented to the multi-board layer chip scale packages (CSP), and its results are discussed.