• ETRI Journal
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• v.30 no.1
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• pp.113-128
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• 2008

Turbo codes are extensively used in current communications standards and have a promising outlook for future generations. The advantages of software defined radio, especially dynamic reconfiguration, make it very attractive in this multi-standard scenario. However, the complex and power consuming implementation of the maximum a posteriori (MAP) algorithm, employed by turbo decoders, sets hurdles to this goal. This work introduces an ASIP architecture for the MAP algorithm, based on a dual-clustered VLIW processor. It displays the good performance of application specific designs along with the versatility of processors, which makes it compliant with leading edge standards. The machine deals with multi-operand instructions in an innovative way, the fetching and assertion of data is serialized and the addressing is automatized and transparent for the programmer. The performance-area trade-off of the proposed architecture achieves a throughput of 8 cycles per symbol with very low power dissipation.

• Journal of information and communication convergence engineering
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• v.8 no.6
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• pp.687-689
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• 2010

In this paper, the equalization for frequency slope of path loss in Multi-Band(MB) OFDM UWB is proposed. The path loss of a signal is proportionate to the square of the signal's frequency. So, the received signal amplitudes of OFDM subcarrier can be different up to 3dB when MB-OFDM occupies bandwidth over 1.5GHz. The differences of subcarrier-amplitudes make an effective of 0.3 bit reduction of soft decision bits of viterbi decoder, and when the effective of 0.3 bit reduction can cause 0.5dB SNR degradation. This paper proposes two modem architectures which compensate for the degraded subcarrier by multiplying the reciprocal of degraded values in analog or digital domain. It is shown that, for the proposed architecture applied to MB-OFDM UWB, the performance improvements up to 0.5dB can be obtained over the conventional uncompensated receiver architecture.

• Annual Conference on Human and Language Technology
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• 2022.10a
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• pp.95-99
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• 2022

오픈 도메인 질의 응답 (ODQA, Open-Domain Question Answering)은 주어진 질문에 대한 답을 찾는 과업으로서 질문과 관련있는 지식을 찾는 "검색" 단계를 필요로 한다. 최근 이미지, 테이블 등의 검색을 요구하는 멀티 모달 ODQA에 대한 연구가 많이 진행되었을 뿐만 아니라 산업에서의 중요도 또한 높아지고 있다. 본 논문은 여러 종류의 멀티 모달 ODQA 중에서도 테이블 - 텍스트 기반 멀티 모달 ODQA 데이터 집합으로 Fusion-in-Decoder (FiD)를 이용한 멀티 모달 오픈 도메인 질의 응답 연구를 제안하며 베이스라인 대비 최대 EM 20.5, F1 23.2 향상을 보였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.6C
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• pp.865-873
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• 2004

MPEG-2 Advanced Audio Coding(AAC) is widely used in the multi-channel audio compression standards. And it combines hi인-resolution filter bank prediction techniques, and Huffman coding algorithm to achieve the broadcast-quality audio level at very low data rates. The forward and inverse modified discrete transforms which are operated in the encoder and the decoder of the filter bank need many computations. In this paper, we propose suitable recursive structure at IMDCT processing for MPEG-2 AAC real-time decoder. We confirm the memory, the computation speed and complexity of the proposed structure.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.9
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• pp.1020-1028
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• 1992

In this paper, a burst-error-correcting adaptive decoding in TCM(Trellis Coded Modulation) is presented that combines maximun-likelihood decoding with a burst error detection scheme. The decoder usually operates as a Viterbi decoder and switches to a burst-error-correcting mode whenever error patterns uncorrectable by Viterbi decoder are detected. It is demonstrated that TCM using adaptive decoding method outperforms a traditional TCM on the multi-path fading channels that are busty in nature, which are like the channel environments of mobile communications.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.18 no.3
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• pp.653-669
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• 2024

Dynamic scene deblurring is a complex computer vision problem owing to its difficulty to model mathematically. In this paper, we present a novel approach for image deblurring with the help of the sharp reference image, which utilizes the reference image for high-quality and high-frequency detail results. To better utilize the clear reference image, we develop an encoder-decoder network and two novel modules are designed to guide the network for better image restoration. The proposed Reference Extraction and Aggregation Module can effectively establish the correspondence between blurry image and reference image and explore the most relevant features for better blur removal and the proposed Spatial Feature Fusion Module enables the encoder to perceive blur information at different spatial scales. In the final, the multi-scale feature maps from the encoder and cascaded Reference Extraction and Aggregation Modules are integrated into the decoder for a global fusion and representation. Extensive quantitative and qualitative experimental results from the different benchmarks show the effectiveness of our proposed method.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.2
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• pp.104-113
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• 2013

A high-throughput Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder architecture is proposed for 60GHz multi-gigabit wireless personal area network (WPAN) applications. Two novel techniques which can apply to our selected QC-LDPC code are proposed, including a four block-parallel layered decoding technique and fixed wire network. Two-stage pipelining and four block-parallel layered decoding techniques are used to improve the clock speed and decoding throughput. Also, the fixed wire network is proposed to simplify the switch network. A 672-bit, rate-1/2 QC-LDPC decoder architecture has been designed and implemented using 90-nm CMOS standard cell technology. Synthesis results show that the proposed QC-LDPC decoder requires a 794K gate and can operate at 290 MHz to achieve a data throughput of 3.9 Gbps with a maximum of 12 iterations, which meet the requirement of 60 GHz WPAN applications.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.10
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• pp.827-832
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• 2013

Holographic data storage system is affected by two dimensional intersymbol interference and inter-page interference. Especially, for multi-level holographic data storage system, since one pixel contains more than 1 bit, the system is more vulnerable to the error. In this paper, we propose a 2/3 modulation code for 4-level holographic data storage system. The proposed modulation code with error correcting capability could be compensated these interferences. Also, in this paper, we proposed a Viterbi decoder for 2/3 modulation code. The proposed Viterbi decoder eliminates unnecessary calculation. As a result, proposed 2/3 modulation code and Viterbi decoder has shown better performance than conventional one.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.12
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• pp.50-56
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• 2016

This paper proposes the architecture and design of intra prediction circuit for a multi-decoder supporting UHD images. The proposed circuit supports not only the latest video compression standard HEVC but also H.264. In addition to the basic function of performing intra prediction, this circuit has the capability of performing the reference sample filter operation defined in the H.264 standard, and the smoothing and strong sample filter operations defined in the HEVC standard. We reduced the circuit size by sharing the circuit blocks for common operations and internal storage, and improved the circuit performance by parallel processing. The proposed circuit was described at RTL using Verilog HDL and its functionality was verified by using NC-Verilog of Cadence. The RTL circuit was synthesized by using Design Compiler of Synopsys and 130nm standard cell library. The synthesized gate-level circuit consists of 69,694 gates and processes 100 ~ 280 frames per second for 4K-UHD HEVC images at the maximum operation frequency of 157MHz.

• Journal of IKEEE
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• v.19 no.1
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• pp.1-9
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• 2015

This paper proposes the design of sub-pixel interpolation circuit for real-time multi-decoder supporting 4K-UHD video images. The proposed sub-pixel interpolation circuit supports H.264, MPEG-4, VC-1 and new video compression standard HEVC. The common part of the interpolation algorithm used in each video compression standard is shared to reduce the circuit size. An intermediate buffer is effectively used to reduce the circuit size and optimize the performance. The proposed sub-pixel interpolation circuit was synthesised by using 130nm standard cell library. The synthesized gate-level circuit consists of 122,564 gates and processes 35~86 image frames per second for 4K-UHD video at the maximum operation frequency of 200MHz. Therefore, the proposed circuit can process 4K-UHD video in real time.