• Title/Summary/Keyword: multi-core CPU

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Development of a Multi-Channel Ultrasonic Testing System for Automated Ultrasonic Pipe Inspection of Nuclear Power Plant (원전 배관 자동 초음파 검사를 위한 다채널 초음파 시스템 개발)

  • Lee, Hee-Jong;Cho, Chan-Hee;Cho, Hyun-Joon
    • Journal of the Korean Society for Nondestructive Testing
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    • v.29 no.2
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    • pp.145-152
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    • 2009
  • Currently almost all in-service-inspection techniques, applied in domestic nuclear power plants, are partial to field inspection technique. These kinds of techniques are related to managing nuclear power plants by the operation of foreign-produced inspection devices. There have been so many needsfor development of native in-service-inspection device because there is no native diagnosis device for nuclear power plant inspection yet in Korea. In this research, we developed several core techniques to make an automated ultrasonic pipe inspection system for nuclear power plants. A high performance multi-channel ultrasonic pulser/receiver module, an A/D converter module and a digital main CPU module were developed and the performance of the developed modules was verified. The S/N ratio, noise level and signal acquisition performance of the developed modules showed proper level as we designed in the beginning.

Metastability Window Measurement of CMOS D-FF Using Bisection (이분법을 이용한 CMOS D-FF의 불안정상태 구간 측정)

  • Kim, Kang-Chul;Chong, Jiang
    • The Journal of the Korea institute of electronic communication sciences
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    • v.12 no.2
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    • pp.273-280
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    • 2017
  • As massive integration technology of transistors has been developing, multi-core circuit is fabricated on a silicon chip and a clock frequency is getting faster to meet the system requirement. But increasing the clock frequency can induce some problems to violate the operation of system such as clock synchronization, so it is very import to avoid metastability events to design digital chips. In this paper, metastability windows are measured by bisection method in H-spice depending on temperature, supply voltage, and the size of transmission gate with D-FF designed with 180nm CMOS process. The simulation results show that the metastability window(: MW) is slightly increasing to temperature and supply voltage, but is quadratic to the area of a transmission gate, and the best area ration of P and Ntransitor in transmission gate is P/N=4/2 to get the least MW.

Implementation of Real-time Data Stream Processing for Predictive Maintenance of Offshore Plants (해양플랜트의 예지보전을 위한 실시간 데이터 스트림 처리 구현)

  • Kim, Sung-Soo;Won, Jongho
    • Journal of KIISE
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    • v.42 no.7
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    • pp.840-845
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    • 2015
  • In recent years, Big Data has been a topic of great interest for the production and operation work of offshore plants as well as for enterprise resource planning. The ability to predict future equipment performance based on historical results can be useful to shuttling assets to more productive areas. Specifically, a centrifugal compressor is one of the major piece of equipment in offshore plants. This machinery is very dangerous because it can explode due to failure, so it is necessary to monitor its performance in real time. In this paper, we present stream data processing architecture that can be used to compute the performance of the centrifugal compressor. Our system consists of two major components: a virtual tag stream generator and a real-time data stream manager. In order to provide scalability for our system, we exploit a parallel programming approach to use multi-core CPUs to process the massive amount of stream data. In addition, we provide experimental evidence that demonstrates improvements in the stream data processing for the centrifugal compressor.

Development of High-Speed Real-Time Signal Processing Unit for Small Radio Frequency Tracking Radar Using TMS320C6678 (TMS320C6678을 적용한 소형 Radio Frequency 추적레이다용 고속 실시간 신호처리기 설계)

  • Kim, Hong-Rak;Hyun, Hyo-Young;Kim, Younjin;Woo, Seonkeol;Kim, Gwanghee
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.21 no.5
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    • pp.11-18
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    • 2021
  • The small radio frequency tracking radar is a tracking system with a radio frequency sensor that identifies a target through all-weather radio frequency signal processing for a target and searches, detects and tracks the target for the major target. In this paper, we describe the development of a board equipped with TMS320C6678 and XILINX FPGA (Field Programmable Gate Array), a high-speed multi-core DSP that acquires target information through all-weather radio frequency and identifies a target through real-time signal processing. We propose DSP-FPGA combination architecture for DSP and FPGA selection and signal processing, and also explain the design of SRIO for high-speed data transmission.

EPAR V2.0: AUTOMATED MONITORING AND VISUALIZATION OF POTENTIAL AREAS FOR BUILDING RETROFIT USING THERMAL CAMERAS AND COMPUTATIONAL FLUID DYNAMICS (CFD) MODELS

  • Youngjib Ham;Mani Golparvar-Fard
    • International conference on construction engineering and project management
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    • 2013.01a
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    • pp.279-286
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    • 2013
  • This paper introduces a new method for identification of building energy performance problems. The presented method is based on automated analysis and visualization of deviations between actual and expected energy performance of the building using EPAR (Energy Performance Augmented Reality) models. For generating EPAR models, during building inspections, energy auditors collect a large number of digital and thermal imagery using a consumer-level single thermal camera that has a built-in digital lens. Based on a pipeline of image-based 3D reconstruction algorithms built on GPU and multi-core CPU architecture, 3D geometrical and thermal point cloud models of the building under inspection are automatically generated and integrated. Then, the resulting actual 3D spatio-thermal model and the expected energy performance model simulated using computational fluid dynamics (CFD) analysis are superimposed within an augmented reality environment. Based on the resulting EPAR models which jointly visualize the actual and expected energy performance of the building under inspection, two new algorithms are introduced for quick and reliable identification of potential performance problems: 1) 3D thermal mesh modeling using k-d trees and nearest neighbor searching to automate calculation of temperature deviations; and 2) automated visualization of performance deviations using a metaphor based on traffic light colors. The proposed EPAR v2.0 modeling method is validated on several interior locations of a residential building and an instructional facility. Our empirical observations show that the automated energy performance analysis using EPAR models enables performance deviations to be rapidly and accurately identified. The visualization of performance deviations in 3D enables auditors to easily identify potential building performance problems. Rather than manually analyzing thermal imagery, auditors can focus on other important tasks such as evaluating possible remedial alternatives.

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Optimizing Multiprecision Squaring for Efficient Public Key Cryptography on 8-bit Sensor Nodes (8 비트 센서 노드 상에서 효율적인 공개키 암호를 위한 다정도 제곱 연산의 최적화)

  • Kim, Il-Hee;Park, Yong-Su;Lee, Youn-Ho
    • Journal of KIISE:Computer Systems and Theory
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    • v.36 no.6
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    • pp.502-510
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    • 2009
  • Multiprecision squaring is one of the most significant algorithms in the core public key cryptography operation. The aim of this work is to present a new improved squaring algorithm compared with the MIRACL's multi precision squaring algorithm in which the previous work [1] on multiprecision multiplication is implemented. First, previous works on multiprecision multiplication and standard squaring are analyzed. Then, our new Lazy Doubling squaring algorithm is introduced. In MIRACLE library [3], Scott's Carry-Catcher Hybrid multiplication technique [1] is applied to implementation of multiprecision multiplication and squaring. Experimental results of the Carry-Catcher hybrid squaring algorithm and the proposed Lazy Doubling squaring algorithm both of which are tested on Atmega128 CPU show that proposed idea has achieved significant performance improvements. The proposed Lazy Doubling Squaring algorithm reduces addition instructions by the fact $a_0\;{\ast}\;2\;+\;a_1\;{\ast}\;2\;+\;...\;+\;a_{n-1}\;{\ast}\;2\;+\;a_n\;{\ast}\;2\;=\;(a_0\;+\;a_1\;+\;...\;+\;a_{n-1}\;+\;a_n)\;{\ast}\;2$ while the standard squaring algorithm reduces multiplication instructions by the fact $S_{ij}\;=\;x_i\;{\ast}\;x_j\;=\;S_{ij}$. Experimental results show that the proposed squaring method is 25% faster than that in MIRACL.