• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.12 no.5
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• pp.123-128
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• 2012

In order to overcome the hardware complexity and performance limit problems, recently the multi-core architecture has been prevalent. For hardware simplicity, usually RISC processor is adopted as the unit core processor. However, if the performance of unit core processor is enhanced, the overall performance of the multi-core processor architecture can be further enhanced. In this paper, in-order superscalar processor is utilized as the core for the multi-core processor architecture. Using SPEC 2000 benchmarks as input, the trace-driven simulation has been performed for the number of superscalar cores between 2 and 16 and the window size of 4 to 16 extensively. As a result, the 16-core superscalar processor for the window size of 16 results in 8.4 times speed up over the single core superscalar processor. When compared with the same number of cores, the multi-core superscalar processor performance doubles that of the multi-core RISC processor.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.297-312
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• 2012

For future multi-core processors, 3D integration is regarded as one of the most promising techniques since it improves performance and reduces power consumption by decreasing global wire length. However, 3D integration causes serious thermal problems since the closer proximity of heat generating dies makes existing thermal hotspots more severe. Conventional air cooling schemes are not enough for 3D multi-core processors due to the limit of the heat dissipation capability. Without more efficient cooling methods such as liquid cooling, the performance of 3D multi-core processors should be degraded by dynamic thermal management. In this paper, we examine the architectural impact of cooling methods on the 3D multi-core processor to find potential benefits of liquid cooling. We first investigate the thermal behavior and compare the performance of two different cooling schemes. We also evaluate the leakage power consumption and lifetime reliability depending on the temperature in the 3D multi-core processor.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.959-962
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• 2009

Recently, a multi-core system is studied for single terminal's operations on various service networks for mobile systems. Therefore, it is expected that mobile systems capable of supporting WCDMA, GSM, and WiBro would be developed. Mobile systems for supporting various service networks is able to be implemented on a single chipset via SoC(System on Chip) technology, thus a noble modem design proper for SoC technology is necessary. As those systems shall be operated at different frequency band with only a single terminal, a problem that a nonlinear characteristic according to the system and its frequency band is occurred. In this paper a noble modem design for multi-core systems is proposed and the nonlinear characteristics for those systems is analysed. The proposed modem design is based on OFDM(Orthogonal Frequency Division Multiplexing) and MC-CDMA scheme. And nonlinear characteristic analysis is done by PSD measurement.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.270-273
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• 2012

In this paper, I present the design of Operational Flight Programs(OFPs) on a Multi-Core based Mission Computer(MC) for the optimized performance of the OFPs on Multi-Core based MC. The program assigned as tasks on Multi-Core environment can be scheduled by designing with the use of OpenMp, which is the standard for parallel programming. This paper also describes the differences between Multi-Core Program(MCP) on the technique and Single-Core Program(SCP) in terms of performance aspect. The new proposed design technique is applied to the Integrated Up-Front Control OFP(IUFC OFP) on General Processor Module where Multi-Core based. This paper describes the Multi-Core design technique for the optimized performance of the IUFC OFP, which display and control flight data(Navigation, Communication, Identification Friend or Foe) to pilot.

• Journal of computational fluids engineering
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• v.16 no.3
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• pp.95-103
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• 2011

In the block type VHTR core, there are inevitable gaps among core blocks for the installation and refueling of the fuel blocks. These gaps are called bypass gap and the bypass flow is defined as a coolant flows through the bypass gap. Distribution of core bypass flow varies according to the reactor operation since the graphite core blocks are deformed by the fast neutron irradiation and thermal expansion. Furthermore, the cross-flow through an interfacial gap between the stacked blocks causes flow mixing between the coolant holes and bypass gap, so that complicated flow distribution occurs in the core. Since the bypass flow affects core thermal margin and reactor efficiency, accurate prediction and evaluation of the core bypass flow are very important. In this regard, experimental and computational studies were carried out to evaluate the core bypass flow distribution. A multi-block experimental apparatus was constructed to measure flow and pressure distribution. Multi-block effect such as cross flow phenomenon was investigated in the experiment. The experimental data were used to validate a CFD model foranalysis of bypass flow characteristics in detail.

• Journal of Advanced Marine Engineering and Technology
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• v.39 no.6
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• pp.604-608
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• 2015

In this paper, we study the characteristics of heat transfer for an insulated multi-core tube using glass wool as an insulator for the multi-core tube. By performing experiments and modeling, we examine the variations in the temperature characteristics of hydraulic oil inside the multi-core tube with atmosphere temperature, inlet temperature, and the flow rate of hydraulic oil for the insulated multi-core tube that we developed. When the minimum inlet flow rate of hydraulic oil employed within the scope of the research is 0.29 l/min, the temperature difference obtained in the experiments and numerical analysis was a maximum of $3^{\circ}C$. For a constant atmospheric temperature, as the inlet temperature of the hydraulic oil increases, the outlet temperature of the hydraulic oil will also increase, regardless of its inlet flow rate. Further, when the inlet flow rate of the hydraulic oil is more than 1.01 l/min, the effect of the atmospheric temperature on the temperature drop of the hydraulic oil is low.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.4
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• pp.251-257
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• 2016

The multi-core technology has become pervasive in embedded systems. An implementation of the Doppler Beam Sharpening algorithm that improves the azimuth resolution by using doppler frequency shift is possible only in multi-core environment because of the amount of calculation. In this paper, we design of multi-core architecture for a real time implementation of DBS algorithm. And based on designed structure, we produce a DBS image on P4080 board.

• Journal of applied mathematics & informatics
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• v.41 no.6
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• pp.1317-1326
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• 2023

Today's computers, desktops and laptops were build with multi-core architecture. Developing and running serial programs in this multi-core architecture fritters away the resources and time. Parallel programming is the only solution for proper utilization of resources available in the modern computers. The major challenge in the multi-core environment is the designing of parallel algorithm and performance analysis. This paper describes the design and performance analysis of parallel algorithm by taking the Knight Tour problem as an example using OpenMP interface. Comparison has been made with performance of serial and parallel algorithm. The comparison shows that the proposed parallel algorithm achieves good performance compared to serial algorithm.

• Journal of Korea Society of Industrial Information Systems
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• v.26 no.5
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• pp.11-19
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• 2021

In this paper, we proposed an asymmetric multi-core processor scheduling scheme which is based on the mileage of each core. We considered a big-LITTLE multi-core processor structure, which consists of low power consuming LITTLE cores with general performance and high power consuming big cores with high performance. If a task needs to be processed, the processor decides a core type (big or LITTLE) to handle the task, and then investigate the core with the shortest mileage among unoccupied cores. Then assigns the task to the core. We developed a mileage-based balancing algorithm for asymmetric multi-core assignment and showed that the proposed scheduling scheme is more cost-effective compared to the traditional scheme from a management perspective. Simulation is also conducted for the purpose of performance evaluation of our proposed algorithm.

• Journal of the Korea Society of Computer and Information
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• v.20 no.9
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• pp.1-10
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• 2015

In this paper, we propose a new variable latency L1 data cache architecture for multi-core processors. Our proposed architecture extends the traditional variable latency cache to be geared toward the multi-core processors. We added a specialized data structure for recording the latency of the L1 data cache. Depending on the added latency to the L1 data cache, the value stored to the data structure is determined. It also tracks the remaining cycles of the L1 data cache which notifies data arrival to the reservation station in the core. As in the variable latency cache of the single-core architecture, our proposed architecture flexibly extends the cache access cycles considering process variation. The proposed cache architecture can reduce yield losses incurred by L1 cache access time failures to nearly 0%. Moreover, we quantitatively evaluate performance, power, energy consumption, power-delay product, and energy-delay product when increasing the number of cache access cycles.