• 전력전자학회:학술대회논문집
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• 전력전자학회 2001년도 Proceedings ICPE 01 2001 International Conference on Power Electronics
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• pp.301-303
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• 2001

In this paper we present a Capacitor Charging Power Supply (CCPS) using a series-resonant three-level inverter topology to improve voltage regulation and use semiconductor switches having low blocking voltage capability such as MOSFETs. This inverter can be operated with two modes, Full Power Mode (FPM) and Half Power Mode (HPM). In FPM inverter supplies the high frequency step up transformer with full DC-link voltage and in HPM with half DC-link voltage. HPM switching method will be adopted when CCPS output voltage reaches the preset target value and operates in refresh mode-charge is maintained on the capacitor. In this topology each semiconductor devices blocks a half of the DC-link voltage[2]. A 15kW, 30kV CCPS has been built and will be tested for an electric precipitator application. The CCPS operates from an input voltage of 500VDC and has a variable output voltage between 10 to 30kV and 1kHz repetition rate at 44nF capacitive load [3]. A resonant frequency of 67.9kHz was selected and a voltage regulation of $0.83\%$ has been achieved through the use of half power mode without using the forced cut off the switch current [1]. The theory of operation, circuit topology and test results are given.

• 제어로봇시스템학회논문지
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• 제13권1호
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• pp.65-71
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• 2007

Adjustable autonomy architecture provides various ways for a human operator to participate as a member of a human-robot team in improving the performance of the team by resolving issues that the robots cannot deal with or performing tasks that the robots alone would unable to do. According to the level of involvement of the human operator, the robots have to adjust their level of autonomy and, in consequence, the operation mode of the overall system shifts. This paper deals with the implementation issues of seamless switching when the level of autonomy of the human-robot team shifts from one level to another. Especially, we focus on developing reliable methods for monitoring the task progress and maximizing the system flexibility by coping with the detailed differences between humans and robots in their characteristics of motions and their choices of positions, paths, and sequences of sub-goals to achieve a given task. To test and motivate the proposed methods, we have assembled three heterogeneous robots which work together to dock both ends of a suspended beam into stanchions.

• 한국통신학회논문지
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• 제25권1B호
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• pp.42-47
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• 2000

버스트 모드 패킷 트래픽 조건에서 스위칭 소광비를 최대화하는 전기 광학 광변조기의 바이어스 안정화를 위한 새로운 방법을 입증하였다. 광변조기의 오프 레벨 출력 전력을 샘플링하고 최소화함으로써 패킷 트래픽 밀도의 변화에 무관하게 높은 소광비를 갖는 광 게이트로서 동작한다

• 전력전자학회논문지
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• 제19권6호
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• pp.488-493
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• 2014

This paper presents a carrier-based pulse-width modulation(PWM) method for reducing the common-mode voltage of a three-level four-leg converter. The idea of the proposed PWM method is intuitive and easy to be implemented in digital signal processor-based converter control systems. On the basis of the analysis of space-vector PWM(SVPWM) and sinusoidal PWM(SPWM) switching patterns, the fourth leg pole voltage of the three-phase converter called "f leg pole voltage" is manipulated to reduce the common-mode voltage. To synthesize f leg pole voltage for the suppression of the common-mode voltage, positive and negative pole voltage references of f leg are calculated. An offset voltage is also deduced to prevent the distortion of a, b, and c phase voltages. The feasibility of the proposed PWM method is verified by simulation and experimental results. The common-mode voltage of the proposed PWM method in peak-to-peak value is 33% in comparison with that of the conventional SVPWM method. The transition number of the common-mode voltage is also reduced to 25%.

• Journal of Power Electronics
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• 제16권4호
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• pp.1316-1323
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• 2016

Multilevel inverters (MLIs) have been preferred over conventional two-level inverters due to their inherent properties such as reduced harmonic distortion, lower electromagnetic interference, minimal common mode voltage, ability to synthesize medium/high voltage from low voltage sources, etc. On the other hand, they suffer from an increased number of switching devices, complex gate pulse generation, etc. This paper develops an ingenious symmetrical MLI topology, which consumes lesser component count. The proposed level dependent sources concoction multilevel inverter (LDSCMLI) is basically a multilevel dc link MLI (MLDCMLI), which first synthesizes a stepped dc link voltage using a sources concoction module and then realizes the ac waveform through a conventional H-bridge. Seven level and eleven level versions of the proposed topology are simulated in MATLAB r2010b and prototypes are constructed to validate the performance. The proposed topology requires lesser components compared to recent component reduced MLI topologies and the classical topologies. In addition, it requires fewer carrier signals and gate driver circuits.

• Journal of Power Electronics
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• 제9권3호
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• pp.481-490
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• 2009

This paper describes a SVPWM overmodulation scheme of NPC type three-level inverter for traction drives which extends the modulation index from MI=0.907 to unity. SVPWM strategy is organized by two operation modes of under-modulation and over-modulation. The switching states under the under-modulation modes are determined by dividing them with two linear regions and one hybrid region the same as the conventional three-level inverter. On the other hand, under the over-modulation mode, they are generated by doing it with two over-modulation regions the same as the conventional over-modulation strategy of a two level inverter. Following the description of over-modulation scheme of a three-level inverter, the system description of a vector controlled induction motor for traction drives has been discussed. Finally, the validity of the proposed modulation algorithm has been verified through simulation and experimental results.

• 한국생물공학회:학술대회논문집
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• 한국생물공학회 2001년도 추계학술발표대회
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• pp.537-540
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• 2001

A parallel TBF system that is consisted of two TBFs was developed f ‘ or the long-term treatment of gas-phase trichloroethylene (TCE). Each TBF was operated for TCE degradation or reactivation in a parallel mode, and the effect of switching time and operation variables between the two reactors was investigated. Within 12 hr after switching from TCE degradation to reactivation mode, the MO activity increased up to the initial level. More than 50 % of TCE was degraded for feed concentrations ranging from 5 to 17 ppmv, and completely 100 % removed at concentration of less than 5 ppmv, while TCE removal decreased severely over 28 ppmv. In various empty bed retention times (EBRTs), ranging 상 om 5.2 to 10.7 min, the optimal EBRT was 10.7 min that TCE conversion achieved more than 50 %. For the inlet loading below 23.4 mg TCE/L/day, TCE was entirely removed. The maximal TCE elimination capacity in this system was about 66.63 mg TCE/L/day. During the continuous treatment of TCE over 3 months, TCE removal efficiency was maintained at the range of about 50 %. In these results, the parallel TBF system can be available for the continuously TCE biodegrading operation.

• 조명전기설비학회논문지
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• 제19권4호
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• pp.71-78
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• 2005

본 연구는 AC PDP(Plasma Display Panel)용 멀티레벨 에너지 회수회로에 관한 연구로서, 기존 멀티레벨 구동회로의 문제점을 해결한 새로운 멀티레벨 구동회로를 제안한다. 기존 멀티레벨 구동회로는 Weber회로에서 나타나는 스위칭 소자의 전압 및 전류 스트레스를 개선하였지만 공진 인덕터와 기생 커패시턴스에 의한 기생공진전류가 존재하고 하드스위칭이 발생하며 또한 천이구간이 다소 긴 문제점이 있다. 제안 회로는 사용소자의 수를 줄여 회로를 간단히 하였으며, 기생공진전류를 제거하여 회로 동작의 안정성을 높였다. 또한 CIM(Current Injection Method) 을 사용하여 하드스위칭 문제를 해결하였으며 Vs/2 유지구간을 제거하여 동작주파수를 증가시킬 수 있도록 하였다. 제안 회로의 유용성을 입증하기 위해 모드별로 동작을 해석하였으며, PSpice프로그램을 이용하여 시뮬레이션하고 그 결과를 확인하였다.

• 전력전자학회논문지
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• 제10권2호
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• pp.194-202
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• 2005

본 연구는 새로운 AC PDP(Plasma Display Panel)용 멀티레벨 에너지 회수회로에 관한 연구로서, 기존 멀티레벨 구동회로의 장점을 그대로 유지하면서 문제점을 해결한 새로운 멀티레벨 구동회로를 제안한다. 기존의 멀티레벨 구동회로는 Weber회로의 하드스위칭 문제를 개선하였지만 공진 인덕터에 기생공진전류가 존재하고 Vs/2유지구간이 존재한다. 제안한 회로는 기존 회로에 비해 인덕터의 수를 반으로 줄여 회로를 간단히 하고 공진 인덕터의 기생 공진전류와 Vs/2유지구간을 제거하였으며 CIM(Current Injection Method)을 사용하여 하드스위칭 문제를 해결하였다. 또한 풀브리지 구동회로에 직렬 연결된 스위칭 소자에 NPC(Neutral Point Clamping)기법을 적용하여 각 스위칭 소자에 전압이 균등하게 분배되도록 하였다. 그리고 제안회로의 동작을 모드별로 해석하였으며, PSpice 프로그램으로 시뮬레이션하고 회로를 구성하여 실험함으로써 제안한 회로의 유용성을 입증하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(5)
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• pp.87-90
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• 2002

This paper describes design technique of switched-capacitor 1V delta-sigma modulator. To solve the incomplete switching operation at low voltage, bootstrapping technique is used. For PMOS input pair of 1V operational amplifier, simple common mode level down technique is used. Designed 2nd order single loop modulator has an oversampling ratio of 64 and obtains a peak SNR of 71dB, a dynamic range of 73 dB with the power consumption of 350uW at 1V power supply.