• Journal of Power Electronics
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• v.18 no.5
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• pp.1315-1324
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• 2018

A novel three-phase four-wire inverter topology is presented in this paper. This topology is equipped with a special capacitor balance grid without magnetic saturation. In response to unbalanced load and unequal split DC-link capacitors problems, a qusi-full-bridge DC/DC topology is applied in the balance grid. By using a high-frequency transformer, the energy transfer within the two split dc-link capacitors is realized. The novel topology makes the voltage across two split dc-link capacitors balanced so that the neutral point voltage ripple is inhibited. Under the condition of a stable neutral point voltage, the three-phase four-wire inverter can be equivalent to three independent single phase inverters. As a result, the three-phase inverter can produce symmetrical voltage waves with an unbalanced load. To avoid forward transformer magnetic saturation, the voltages of the primary and secondary windings are controlled to reverse once during each switching period. Furthermore, an improved mode chosen operating principle for this novel topology is designed and analyzed in detail. The simulated results verified the feasibility of this topology and an experimental inverter has been built to test the power quality produced by this topology. Finally, simulation results verify that the novel topology can effectively improve the inhibition of an inverter with a three-phase unbalanced load while decreasing the value of the split capacitor.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.14 no.3
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• pp.6-14
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• 2000

The high efficiency multi-resonant converter(MRC) is capable of operating at a high frequency because the losses are decreased due to the resonant tank circuit. Such a few MHz high frequency applications provide high power density[W/inch3] of the converter. However, the resonant voltage stress across the switch of the resonant tank circuit is 4∼5 times input voltage. This high voltage stress increases the conduction losses because of on-resistance of a MOSFET with higher rating. In this paper, the modeling analysis for the AT Forward MRC suggested to solve the these problems is discusses. The operational modes of the AT Forward MRC are divided to 8 equivalent modes according to the two switching sequences. Each mode analysis is covered using the equivalent circuits modeled over all of the paper. The operational principle of the resonant converter was verified through the experimental converter with 48[V] input voltage, 5[V]/50[W] output voltage/power and PSpice simulation. The measured maximum voltage, 5[V]/50[W] output voltage/power and PSpice simulation. The measure maximum voltage stress is 170[V] of 2.9 times the input voltage and the maximum efficiency is measured to 81.66%.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.20 no.8
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• pp.36-41
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• 2006

Computer Loads can be found in all of modern society. The switching mode power supplies used in personal computers are major sources of harmonic currents. Harmonic currents can cause lots of harmonic problems such as disruption in computer performance. A series resonant filter is very effective in harmonic reduction for personal computer loads. Voltage sags are short duration reductions in rms voltage. The main causes of voltage sags at faults, motor starting, and transformer energizing. Personal computers are another example of devices sensitive to voltage sags. A serious voltage sag at the terminals way lead mis-operation of the equipment. This paper presents an in depth analysis to evaluate the effect of harmonics reduction based on the IEC 61000-3-2 and the effect of voltage sag using ITI curve by applying a series resonant filter for personal computer loads.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.24 no.4
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• pp.81-94
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• 2010

This paper presents a high efficiency resonant asymmetrical half-bridge flyback converter. The primary half-bridge circuit of the converter operates by a soft-switching type using the asymmetrical pulse-width modulation (PWM) method with the resonant capacitance and transformer leakage inductance. The secondary flyback circuit of the proposed converter utilizes a synchronous rectifier, which operates by a new voltage-driven method with a simple drive circuit. Thus the proposed converter improves the total efficiency. This paper explains the operational principle of the proposed converter by each mode and shows the converter design consideration and a design example for the prototype converter, respectively. After that, the proposed simple driving technique of the synchronous rectifier by a voltage-driven method is explained, briefly. The designed prototype converter has wide input voltage (AC $V_{in,rms}$=75~265[V]), 5[V] DC output voltage, and 100[W] output power. To verify the excellent performance of the proposed converter, the designed prototype is implemented and experimented. The good performance of the proposed converter is shown through the experimental results.

• Journal of Advanced Navigation Technology
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• v.24 no.2
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• pp.107-114
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• 2020

A power amplifier of 2.4 GHz ISM band is designed to implement a transmitter system. High efficiency amplifiers can be implemented as class E or class F amplifiers. This study has designed a 20 W high efficiency class E amplifier that has simple circuit structure in order to utilize for the ISM band application. The impedance matching circuit was designed by class E design theory and circuit simulation. The designed amplifier has the output power of 44.2 dBm and the power added efficiency of 69% at 2.45 GHz. In order to apply 30 dBm input power to the designed power amplifier, voltage controlled oscillator (VCO) and driving amplifier have been fabricated for the input feeding circuit. The measurement of the power amplifier shows 43.2 dBm output and 65% power added efficiency. This study can be applied to the design of power amplifiers for various wireless communication systems such as wireless power transfer, radio jamming device and high power transmitter.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.4 no.2
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• pp.307-312
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• 2000

Asynchronous transfer mode(ATM) is flexible to support the various multimedia communication services such as data, voice, and image by applying asynchronous time-sharing and statistical multiplexing techniques to the existing data communication. ATM service is categorized to CBR, VBR, UBR, and ABR according to characteristics of the traffic and a required service qualities. Among them, ABR service guarantees a minimal bandwidth and can transmit cells at a maximum transmission rate within the available bandwidth. To minimize the cell losses in transmission and switching, a feedback information in ATM network is used to control the traffic. In this paper, predictive control algorithms are proposed for the feedback information. When the feedback information takes a long propagation delay to the backward nodes, ATM switch can experience a congestion situation from the queue length increases, and a high queue length fluctuations in time. The control algorithms proposed in this paper provides predictive control model using slop changes of the queue length function and previous data of the queue lengths. Simulation shows the effectiveness result of the proposed control algorithms.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.8
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• pp.1734-1740
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• 2012

In this paper, we propose a FSOURCE circuit which requires such a small switching current that an eFuse OTP memory can be programmed in the post-package state of the PMIC chips using a single power supply. The proposed FSOURCE circuit removes its short-circuit current by using a non-overlapped clock and reduces its maximum current by reducing the turned-on slope of its driving transistor. Also, we propose a DOUT buffer circuit initializing the output data of the eFuse OTP memory with arbitrary data during the power-on reset mode. We design a 24-bit differential paired eFuse OTP memory which uses Magnachip's $0.35{\mu}m$ BCD process, and the layout size is $381.575{\mu}m{\times}354.375{\mu}m$($=0.135mm^2$).

• The Transactions of the Korean Institute of Power Electronics
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• v.20 no.3
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• pp.214-222
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• 2015

The superiority of gallium nitride FET (GaN FET) over silicon MOSFET is examined in this paper. One of the outstanding features of GaN FET is low reverse-recovery charge, which enables continuous conduction mode operation of totem-pole bridgeless boost power factor correction (PFC) circuit. Among many bridgeless topologies, totem-pole bridgeless shows high efficiency and low conducted electromagnetic interference performance, with low cost and simple control scheme. The operation principle, control scheme, and circuit implementation of the proposed topology are provided. The converter is driven in two-module interleaved topology to operate at a power level of 5.5 kW, whereas phase-shedding control is adopted for light load efficiency improvement. Negative bias circuit is used in gate drivers to avoid the shoot-through induced by high speed switching. The superiority of GaN FET is verified by constructing a 5.5 kW prototype of two-module interleaved totem-pole bridgeless boost PFC converter. The experiment results show the highest efficiency of 98.7% at 1.6 kW load and an efficiency of 97.7% at the rated load.

• The Transactions of the Korean Institute of Power Electronics
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• v.14 no.6
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• pp.496-503
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• 2009

In this paper, a new three-phase interleaved isolated high efficiency boost dc-dc converter with active clamp is proposed. The converter is capable of increased power transfer due to its three-phase power configuration, and it reduces the rms current per phase, thus reducing conduction losses. Further, interleaved operation of three-phase boost converter reduces overall ripple current, which is imposed into fuel cells and realizes smaller sized filter components, increasing effective operating frequency and leading to higher power density. Each output current of three-phase boost converter is combined by the three-phase transformer and flows in the continuous conduction mode by the proposed three-phase PWM strategy. An efficiency of above 96% is mainly achieved by reducing conduction losses and switching losses are reduced by the action of active clamp branches, as well. The proposed converter and three-phase PWM strategy are analyzed, simulated and implemented in hardware. Experimental results are obtained on a 500 W prototype unit, with all of the design verified and analyzed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.42 no.2
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• pp.291-298
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• 2017

In this paper, we derive the achievable degrees of freedom (DoF) for multiple-input multiple-output (MIMO) Z-interference channels (Z-IC) with reconfigurable antennas at the receivers, assuming that channel state information is not available at the transmitters. We propose a new linear scheme to align interfering signals and to decode desired signals through the designed preset mode switching pattern of reconfigurable antennas at the receivers. The key idea of our scheme is to use interfering signals as a side information at the interfered receiver by being silent at the corresponding transmitter during some time slots. Consequently, it is shown that the reconfigurable antennas at the receivers can bring a DoF gain if the number of preset modes is greater than the number of RF chains at the receivers.