• The Transactions of the Korean Institute of Power Electronics
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• v.18 no.6
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• pp.579-586
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• 2013

This paper proposes a mode transition algorithm between the grid-tied and the stand-alone operations for the single-phase inverter with the energy storage system. For the grid-tied operation, the dc-link voltage and the output current are required to be control. For the stand-alone mode, both the output voltage and the output current should be regulated. In order to mitigate a falling-off in control performance during transients in mode change, the load power estimation and the current selection schemes are proposed. The proposed method allows an optimized current reference is selected to reduce an output voltage drop and an excessive over-current in transient. To verify the effectiveness of the proposed method, both the simulation and the experiments for a 3kW single-phase inverter with the energy storage system have been conducted. From the results, it has been confirmed that the proposed method reduces a transient error as well as implementing smooth mode transition.

• Journal of Power Electronics
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• v.15 no.5
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• pp.1329-1337
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• 2015

By placing distributed generation power sources beside a big nonlinear load, these sources can be used as a power quality enhancer, while injecting some active power to the network. In this paper, a new scheme to use the distributed generation power source in both operation modes is presented. In this scheme, a fuzzy controller is added to adjust the optimal set point of inverter between compensating mode and maximum active power injection mode, which works based on the harmonic content of the nonlinear load. As the high order current harmonics can be easily rejected using passive filters, the DG is used to compensate the low order harmonics of the load current. Multilevel transformerless cascade inverters are preferred in such utilization, as they have more flexibility in current/voltage waveform. The proposed scheme is simulated in MATLAB/SIMULINK to evaluate the circuit performance. Then, a 1kw single phase prototype of the circuit is used for experimental evaluation of the paper. Both simulative and experimental results prove that such a circuit can inject a well-controlled current with desired harmonics and THD, while having a smaller switching frequency and better efficiency, related to previous 3-phase inverter schemes in the literature.

• Journal of Power Electronics
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• v.19 no.1
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• pp.254-264
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• 2019

This paper proposes an indirect current control technique based on a proportional resonant (PR) approach for the seamless mode transfer of utility interactive inverters. Direct-current and voltage hybrid control methods have been used for inverter control under grid-connected and islanded modes. A large bandwidth can be selected due to the structure of single-loop control. However, this results in poor dynamic transients due to sudden changes of the controller during mode changes. Therefore, inverter control based on indirect current is proposed to improve the dynamic transients by consistently controlling the output voltage under all of the operation modes. A PR-based indirect current control topology is used in this study to maintain the load voltage quality under all of the modes. The design processes of the PR-based triple loop are analyzed in detail while considering the system stability and dynamic transients. The mode transfer techniques are described in detail for both sudden unintentional islanding and islanded mode voltage quality improvements. In addition, they are described using the proposed indirect control structure. The proposed method is verified by the PSiM simulations and laboratory-scale VDER-HILS experiments.

• Journal of Power Electronics
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• v.18 no.3
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• pp.923-930
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• 2018

Based on the application of an integrated dynamic brake (IDB) system that uses a PWM inverter fed-AC motor drive to operate the piston, a new active zero state PWM (AZSPWM) is proposed to improve the stability and reliability of the IDB system by suppressing the conducted electro-magnetic interference (EMI) noise under a wide range of load torque. The new AZSPWM reduces common-mode voltage (CMV) by one-third when compared to that of the conventional space vector PWM (CSVPWM). Although this method slightly increases the output current ripple by reducing the CMV, like the CSVPWM, it can be used within the full range of the load torque. Further, unlike other reduced common-mode voltage (RCMV) PWMs, it does not increase the switching power loss. A theoretical analysis is presented and experiments are performed to demonstrate the effectiveness of this method.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.3
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• pp.509-515
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• 2009

When a squirrel cage induction motor is loaded, the magnetic noise can increase depending on the load current. It is due to the variation of air gap harmonic fluxes from the rotor current induced by loading. This unfavorable noise can be anticipated by analysing the radial force waves in the air gap, the mode shapes of them, and stator core natural frequencies at each mode. With the experimental tests with the different rotor slot numbers, the variation of magnetic noise depending on the load current is studied and the method to reduce the magnetic noise is suggested with the newly developed magnetic noise analysis program.

• Journal of Power Electronics
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• v.12 no.5
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• pp.689-698
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• 2012

This paper investigates the effects of applying different input current waveshapes on the performance of a continuous-conduction-mode (CCM) power-factor-correction (PFC) boost pre-regulator. It is found that the output voltage ripple of the pre-regulator can be reduced if the input current is modified to include controlled amount of higher order harmonics. This finding allows us to balance the performance of output regulation and the harmonic current emission when coming to the design of the pre-regulator. An experimental PFC boost pre-regulator prototype is constructed to verify the analysis and show the benefit of the pre-regulator operating with input current containing higher order harmonics.

• The Transactions of the Korean Institute of Power Electronics
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• v.26 no.1
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• pp.53-58
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• 2021

Operation of the interleaved Boost PFC converter in Critical Conduction Mode (CrM) shows the advantages of high efficiency and good EMI characteristics owing to the valley switching of FET. However, when it is designed for a highly pulsating load, operation at a relatively high frequency is inevitable at non-pulsating typical load condition, resulting in efficiency degradation. Moreover, the physical size of the inductor becomes problematic because of the nature of the CrM operation, where the inductor peak current is about two times the inductor average current, thereby requiring high DC-bias characteristics, which is worse when the output power is high. In this study, a new parallel driving method of two sets of interleaved boost PFC converters for highly pulsating high-power application is proposed. The proposed method does not require any additional load-sharing controller, resulting in high efficiency and smaller inductor size.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.40 no.5
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• pp.479-488
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• 1991

A novel three-phase quasi-resonant dc link inverter (QRI)with a switch connected between dc voltage source and resonant inductor is proposed. According to the state of switching and load current, the operating mode of the proposed inverter scheme is classified into free-wheeling, inverting, and rectifying mode. By examining the behavior of the circuit in each operating mode, an equivalent circuit which represents all the modes in a unified manner is derived. The operating principle of QRI at inverting mode is analyzed, and it is shown that the maximum voltage of resonant dc link is confined to twice the dc source voltage and that both the zero voltage switching of inverter and the zero current switching of inserted switch are guaranteed. An appropriate current control algorithm is suggested, and the opeating characteristics of proposed resonant inverter are verified through both simulation and experiment.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.10
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• pp.40-47
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• 2016

In this paper, a dual mode buck converter with an ability to change mode is proposed, which is suitable particularly for portable device. The problem of conventional mode control circuit is affected by load variation condition such as suddenly or slowly. To resolve this problem, the mode control was designed with slow clock method. Also, when change from the PFM(Pulse Frequency Modulation) mode to the PWM(Pulse Width Modulation) mode, to use the counter to detect a high load. And the user can select mode transition point in load range from 20mA to 90mA by 3 bit digital signal. The circuits are implemented by using BCDMOS 0.18um 2-polt 3-metal process. Measurement environment are input voltage 3.7V, output voltage 1.2V and load current range from 10uA to 500mA. And measurement result show that the peak efficiency is 86% and ripple voltage is less 32mV.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.3
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• pp.59-66
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• 2015

In this paper, we propose a method of improving the light-load efficiency of DC-DC buck converter using 4bit SAR-ADC (Successive Approximation ADC) for a LDO or a power transistor size selection technique. The proposed circuit selects power transistor sizes depending on load current so that improves the light-load efficiency of the DC-DC buck converter. For this, we select the power transistor size with a cross point of the switching loss and the conduction loss. Also, when the IC operates in standby mode or sleep mode, a LDO mode is selected for improving the efficiency. The proposed circuit selects power transistor sizes(X1, X2, X4, X8) with 4 bits and its efficiency is higher about the maximum of 25% at the light-load than that of a single transistor size. Input voltage and output voltage are 5V and 3.3V for maximum load currents of 500mA.