• Title/Summary/Keyword: mobile application processor

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An Implementation of Mobile Gateway Based on Android Smartphone (안드로이드 스마트폰 기반의 모바일 게이트웨이 구현)

  • Lee, Donggeon;Lim, Jae-Hyun
    • Journal of Digital Convergence
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    • v.12 no.1
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    • pp.333-338
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    • 2014
  • Zigbee is a wireless communication technology optimized for WSN (Wireless Sensor Network) environment. A WSN gateway is used for node control and data transmission. However, a fixed-type gateway can restrict the flexibility of the WSN environment. A smartphone-mounted high-performance processor and Android OS can be easily used in a mobile WSN gateway. In this paper, we proposed a mobile WSN gateway based on Android smartphones. In the proposed system, a Zigbee sensor module is connected with a smartphone via USB (Universal Serial Bus) port. We also implemented an Android application for the mobile WSN gateway.

Design of Stand-alone AI Processor for Embedded System (독립운용이 가능한 임베디드 인공지능 프로세서 설계)

  • Cho, Kwon Neung;Choi, Do Young;Jeong, Young Woo;Lee, Seung Eun
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2021.05a
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    • pp.600-602
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    • 2021
  • With the development of the mobile industry and growing interest in artificial intelligence (AI) technology, a lot of research for AI processors which applicable to embedded systems is under study. When implementing AI to embedded systems, the design should be considered the restriction of resource and power consumption. Moreover, it is efficient to include a dedicated hardware accelerator in order to complement the low computational performance of the embedded system. In this paper, we propose an stand-alone embedded AI processor. The proposed AI processor includes a hardware accelerator that is dedicated to the distance-based AI algorithm and a general-purpose MCU that supports flexible programmability for application to various embedded systems. The AI processor was designed with Verilog HDL and verified by implementing on Field Programmable Gate Array (FPGA).

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Design of Bluetooth based MMORPG Game in MANETs (모바일 애드-혹 망에서 Bluetooth 기반 MMORPG의 설계)

  • Oh, Sun-Jin
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.9 no.4
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    • pp.39-45
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    • 2009
  • With the rapid growth of recent wireless mobile computing application technology and handheld mobile terminal device development technology, one of the big issue in these fields is to design online games in wireless mobile ad hoc network environment. Online games in mobile computing environment have lots of constraints for developing online games because mobile terminals have many limitations such as low performance of processor, limited memory space, small bandwidth of wireless communication, and confined life of battery power. Therefore, most of mobile games are restrictive in the function of online and multi-play up to date. In this paper, the online MMORPG game, capable of multi-play with many other mobile users using mobile terminals in wireless mobile computing environment, is designed and implemented. Proposed mobile online game uses bluetooth to construct temporary wireless mobile ad hoc network with other mobile clients, and designed to carry out online MMORPG game with these clients. It also supports multi-play among them.

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Design of Floating-Point Multiplier for Mobile Graphics Application (모바일 그래픽스 응용을 위한 부동소수점 승산기의 설계)

  • Choi, Byeong-Yoon;Salcic, Zoran
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.12 no.3
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    • pp.547-554
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    • 2008
  • In this paper, two-stage pipelined floating-point multiplier (FP-MUL) is designed. The FP-MUL processor supports single precision multiplication for 3D graphic APIs, such as OpenGL and Direct3D and has area-efficient and low-latency architecture via saturated arithmetic, area-efficient sticky-bit generator, and flagged prefix adder. The FP-MUL has about 4-ns delay time under $0.13{\mu}m$ CMOS standard cell library and consists of about 7,500 gates. Because its maximum performance is about 250 MFLOPS, it can be applicable to mobile 3D graphics application.

Efficient Kernel Integrity Monitor Design for Commodity Mobile Application Processors

  • Heo, Ingoo;Jang, Daehee;Moon, Hyungon;Cho, Hansu;Lee, Seungwook;Kang, Brent Byunghoon;Paek, Yunheung
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.15 no.1
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    • pp.48-59
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    • 2015
  • In recent years, there are increasing threats of rootkits that undermine the integrity of a system by manipulating OS kernel. To cope with the rootkits, in Vigilare, the snoop-based monitoring which snoops the memory traffics of the host system was proposed. Although the previous work shows its detection capability and negligible performance loss, the problem is that the proposed design is not acceptable in recent commodity mobile application processors (APs) which have become de facto the standard computing platforms of smart devices. To mend this problem and adopt the idea of snoop-based monitoring in commercial products, in this paper, we propose a snoop-based monitor design called S-Mon, which is designed for the AP platforms. In designing S-Mon, we especially consider two design constraints in the APs which were not addressed in Vigilare; the unified memory model and the crossbar switch interconnect. Taking into account those, we derive a more realistic architecture for the snoop-based monitoring and a new hardware module, called the region controller, is also proposed. In our experiments on a simulation framework modeling a productionquality device, it is shown that our S-Mon can detect the rootkit attacks while the runtime overhead is also negligible.

Design of Chip Set for CDMA Mobile Station

  • Yeon, Kwang-Il;Yoo, Ha-Young;Kim, Kyung-Soo
    • ETRI Journal
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    • v.19 no.3
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    • pp.228-241
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    • 1997
  • In this paper, we present a design of modem and vocoder digital signal processor (DSP) chips for CDMA mobile station. The modem chip integrates CDMA reverse link modulator, CDMA forward link demodulator and Viterbi decoder. This chip contains 89,000 gates and 29 kbit RAMs, and the chip size is $10 mm{\times}10.1 mm$ which is fabricated using a $0.8{\mu}m$ 2 metal CMOs technology. To carry out the system-level simulation, models of the base station modulator, the fading channel, the automatic gain control loop, and the microcontroller were developed and interfaced with a gate-level description of the modem application specific integrated circuit (ASIC). The Modem chip is now successfully working in the real CDMA mobile station on its first fab-out. A new DSP architecture was designed to implement the Qualcomm code exited linear prediction (QCELP) vocoder algorithm in an efficient way. The 16 bit vocoder DSP chip has an architecture which supports direct and immediate addressing modes in one instruction cycle, combined with a RISC-type instruction set. This turns out to be effective for the implementation of vocoder algorithm in terms of performance and power consumption. The implementation of QCELP algorithm in our DSP requires only 28 million instruction per second (MIPS) of computation and 290 mW of power consumption. The DSP chip contains 32,000 gates, 32K ($2k{\times}16\;bit$) RAM, and 240k ($10k{\times}24\;bit$) ROM. The die size is $8.7\;mm{\times}8.3\;mm$ and chip is fabricated using $0.8\;{\mu}m$ CMOS technology.

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The solution for real time interrupt in Xen-ARM to adapt to mobile phones (Xen-ARM의 모바일폰 적용을 위한 실시간 인터럽트 처리 필요성 및 해결방안)

  • Jo, Jae-Hyun;Yoo, See-Hwan;Kwak, Kuen-Hwan;Yo, Chuck
    • Proceedings of the Korean Information Science Society Conference
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    • 2011.06a
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    • pp.516-519
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    • 2011
  • 현재 모바일 폰은 실시간 운영체제를 구동하는 CP(Communication Processor)와 범용 운영체제를 구동하는 AP(Application Processor}, 두 개의 프로세서를 사용하고 있다 임베디드 가상화는 하나의 칩 위에 실시간 운영체제와 범용 운영체제를 동시에 동작시킬 수 있는 솔루tus을 제공하면서, 각각의 운영체제가 서로 고립되어 동작하도록 한다. 따라서 임베디드 가상화 솔루션을 모바일 폰에 적용하면 하나의 집을 사용하여 비용을 절약하면서, 하이퍼바이저 위에 고립된 각각의 운영체제를 구동할 수 있기 때문에 각광을 받고 있다. Xen-ARM 은 모바일 기기에서 가장 많이 사용되는 ARM 프로세서에서 동작하는 하이퍼바이저로 임베디드 기기의 탑재를 목적으로 개발되었다. 그러나 현재의 Xen-ARM의 크레딧 스케쥴러는 CPU 공평성에 포커스를 맞추고 있어 실시간 IO를 제한된 시간 안에 처리할 수 없기 때문에, 실시간 IO를 처리해야 하는 임베디드 기기에 적용하기 어렵다. 본 논문에서는 현재 Xen-ARM이 실시간 IO를 지원할 수 없는 것을 실험을 통해 보여주고, 실시간 IO를 지원하기 위한 방안을 제시한다. 또한 수정된 Xen-ARM을 모바일 폰에 적용하는 방안에 대해 제시한다.

Development of Embedded X-System (임베디드 X-시스템 개발)

  • Jeong, Gab-Joong
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2008.05a
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    • pp.641-644
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    • 2008
  • This paper describes the GUI implementation of an intelligent embedded system which can be used for a personal information platform and an industrial mobile application system. It shows the architecture and the necessary structure and components of X Window graphic system. The embedded system used in this paper has low power and high performance processor, and has a large memory size with a nand-flash memory device. We configured the linux kernel with a TIT-LCD and touch screen device for the operation of X Window system. And we used GTK+2 for running application softwares on the platform embedded system. The GUI library of GTK+2 is useful for providing the same graphics programming environment with host Linux PC. We have developed in this paper the X Window system and the GUI environment for GTK+2 in a new embedded system, and verified the full operation of X Window system and application softwares using GTK+2. The embedded system with large memory size can be used in X Window application softwares for providing a personal information service with a mobile embedded system.

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A Code-level Parallelization Methodology to Enhance Interactivity of Smartphone Entertainment Applications (스마트폰 엔터테인먼트 애플리케이션의 상호작용성 개선을 위한 코드 수준 병렬화 방법론)

  • Kim, Byung-Cheol
    • Journal of Digital Convergence
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    • v.13 no.12
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    • pp.381-390
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    • 2015
  • One of the fundamental requirements of entertainment applications is interactivity with users. The mobile device such as the smartphone, however, does not guarantee it due to the limit of the application processor's computing power, memory size and available electric power of the battery. This paper proposes a methodology to boost responsiveness of interactive applications by taking advantage of the parallel architecture of mobile devices which, for instance, have dual-core, quad-core or octa-core. To harness the multi-core architecture, it exploits the POSIX thread, a platform-independent thread library to be able to be used in various mobile platforms such as Android, iOS, etc. As a useful application example of the methodology, a heavy matrix calculation function was transformed to a parallelized version which showed around 2.5 ~ 3 times faster than the original version in a real-world usage environment.

DSP-Based Micro-Modem for Underwater Acoustic Communications (DSP 기반 초소형 수중 음향통신 모뎀)

  • Lee, Dongsoo;Lee, Sangmin;Park, Sung-Joon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.39C no.3
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    • pp.275-281
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    • 2014
  • Recently, the need for various underwater application systems targeting efficient resource exploration and aquatic ecosystem monitoring is rapidly increasing in littoral sea and inland waters. In this paper, we focus on the research and development of digital module of acoustic micro modem which can be used for underwater mobile communication systems and underwater sensor network systems. Specifically, a digital module of acoustic modem embedding digital signal processor is designed and implemented. On top of the developed hardware platform, physical layer frame generation and recovery and channel coding algorithms are mounted and tested in a water tank and a pond to verify its functionality and performance. According to experimental results, less than 1 percent of total computational power is consumed in the processing of frame control and convolutional code with the data rate of 1 kbps. Thus, the performance of micro modem could be improved by loading efficient baseband algorithms into the processor while maintaining the implemented hardware.