• Progress in Superconductivity
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• v.5 no.1
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• pp.13-16
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• 2003

In this work, we have studied about an RSFQ (Rapid Single Flux Quantum) switch element. The circuit was designed, simulated, and laid out for mask fabrication. The switch cell was composed of a D flip-flop, a splitter, a confluence buffer, and a switch core. The switch core determined if the input data could pass to the output. “On” and o“off” controls in the switch core could be possible by utilizing an RS flip-flop. When a control pulse was input to the “on” port, the RS flip-flop was in the set state and passed the input pulses to the output port. When a pulse was input to the “off” port, the RS flip-flop was in the reset state and prevented the input pulses from transferring to the output port. We simulated and optimized the switch element circuit by using Xic, WRspice, and Julia. The minimum circuit margins in simulations were more than $\pm$20%. We also performed the mask layout of the circuit by using Xic and Lmeter.

• 한국태양에너지학회:학술대회논문집
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• 2008.11a
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• pp.36-41
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• 2008

In this paper, we study The Effects of PV Cell's Electrical Characteristics for PV Module Application. Photovoltaic module consists of serially connected solar cell which has low open circuit voltage and high short circuit current characteristics. The whole current flow of PV module is restricted by lowest current of one solar cell. For the experiment, we make PV module composing the solar cells that have short circuit current difference of 0%, 1%, 3% and Random. The PV module exposed about 35days, its the maximum power drop ratio was 4.282% minimum and 6.657% maximum. And PV module of low current characteristics has electrical stress from other modules. The solar cell temperature of PV module was higher compared to PV cell. To prevent early degradation, it is need to have attention to PV cell selection.

• Proceedings of the KIPE Conference
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• 2001.10a
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• pp.703-707
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• 2001

The demand for protection of power electronic applications has during the last couple of years increased regarding the high-power IGBT modules. Even with an active protection, a high power IGBT still has a risk of exhibiting a violent rupture in the case of a fault if IGBT Fuses do not protect it. By introducing fuses into the circuit this will increase the circuit inductance and slight increase the over-voltage during the turn-off of the diode and the IGBT. It is therefore vital when using fuses that the added inductance is kept at a minimum. This paper discuss three issues regarding the IGBT Fuse protection. First, the problem of adding inductance of existing High-Speed and new Typower fuses in DC-link circuit is treated, second a short discussion of the protection of the IGBT module is done, and finally, the impact of the high frequency loading on the current carrying capability of the fuses is presented.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.3
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• pp.176-185
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• 1996

Transformin the huge size of drawings into a suitable format for CAD system and recognizng the contents of drawings are the major concerans in the automated analysis of engineering drawings. This paper proposes some methods for text/graphics separation, symbol extraction, vectorization and symbol recognition with the object of applying them to electronic cirucit drawings. We use MBR (Minimum bounding rectangle) and size of isolated region on the drawings for separating text and graphic regions. Characteristics parameters such as the number of pixels, the length of circular constant and the degree of round shape are used for extracting loop symbols and geometric structures for non-loop symbols. To recognize symbols, nearest netighbor between FD (foruier descriptor) of extractd symbols and these of classification reference symbols is used. Experimental results show that the proposed method can generate compact vector representation of extracted symbols and perform the scale change and rotation of extracted symbol using symbol vectorization. Also we achieve an efficient searching of circuit drawings.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.3
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• pp.360-371
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• 1993

Flood search algorithm is known to be an effective routing mechanism for tactical application, since it provides high degree of survivability and robustness. But it is known that it has significant drawbacks with respect to the network efficiency [1]. We consider a tactical circuit-switched grid network with a maximum of four links and two priority classes of voice traffic, Using the minimum first-derivative length (MFDL) path, we improve the blocking probability performance of the circuit-switched network without increasing the call set-up time and processor loading of the algorithm.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.923-926
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• 2003

This paper presents a novel low voltage reference circuit under the MOS threshold voltage(V$_{th}$) in standard CMOS process. It is based on the weighted difference of the gate-source voltages of an NMOS and a PMOS operating in saturation region. The voltage reference is designed for low power OLED driver ICs. The proposed circuit is designed using 0.35${\mu}{\textrm}{m}$ CMOS technology. The minimum supply voltage is 2V, and the typical temperature coefficient is 99.6ppm/ C.C.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.6
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• pp.1068-1073
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• 1987

Traditional circuit partitioning algorithm using the cluster development method, which is suitable for such applications as single chip floor planning or multiple layer PCB system placement, where the clusters are formed so that inter-cluster nets are localized within the I/O connector pins, may not be appropriate for the functiona block placement in truly 3-D electronic modules. 3-D hybrid IC is one such example where the inter-layer routing as well as the intra-layer routing can be maximally incorporated to reduce the overall circuit size, cooling requirements and to improve the speed performance. In this paper, we propose a new algorithm called MBE(Minimum Box Embedding) for the layer assignment of each functional block in 3-D hybrid IC design. The sequence of MBE is as follows` i) force-directed relaxation in 3-D space, ii) exhaustive search for the optimal orientation of the slicing plane and iii) layer assignment. The algorithm is first explaines for a 2-D reduced problem, and then extended for 3-D applications. An example result for a circuit consisting of 80 blocks has been shown.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.388-391
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• 1999

This Paper presents an efficient algorithm that minimizes the area of the combinational system through cell replacement. During the minimization, it maintains the circuit speed same. For the minimization, the proposed algorithm defines the criticality of each cell, based on the critical delay and the number of paths passing through the cell. Then, it visits the cells of the system, one by one, from the one with the lowest criticality, and replaces it with the minimum area cell that satisfies the delay constraint. Experimental results, using the LGsynth91 benchmark circuits synthesized by misII, show that the proposed algorithm reduces the circuit area further by 17.54% on the average without sacrificing the circuit speed.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.12
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• pp.2257-2261
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• 2007

A new CMOS transresistance amplifier for low-voltage analog integrated circuit design applications is presented. The proposed transresistance amplifier circuit based on common-source and negative feedback topology is compared with other recent reported transresistance amplifier. The proposed transresistance amplifier achieves high transresistance gain, gain-bandwidth with the same input/output impedance and the minimum supply voltage $2V_{DSAT}+V_T$. Hspice simulation using 1.8V TSMC $0.18{\mu}m$ CMOS technology was performed and achieved $59dB{\Omega}$ transresistance gain which is above the maximum about $18dB{\Omega}$ compared to transresistance gain of the reported circuit.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.8 no.3
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• pp.91-95
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• 1983

The purpose of this paper is to realize an ideal F.D.N.R using a minimum number of passive elements and two CCIIs. The configuration of proposed circuit can be shown to be superior to that of conventional circuit because both capacitors are grounded and may also be equal-valued for easy IC fablication. Experimental data reveals performance of the new circuit for frequency characteristics when appling to an active elliptic low pass filter.