• 마이크로전자및패키징학회지
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• 제13권1호통권38호
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• pp.43-49
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• 2006

새로운 잔류 기공 추출 공정을 적용하여 Blind via hole(BVH)의 형상에 따라 발생되는 잔류기공 특성, 거동 및 신뢰성평가를 수행하였다. 잔류 기공 추출 공정을 적용한 시편에서는 잔류기공이 완전히 제거 되었으며, 기존 공정으로 제조된 시편에 비하여 40% 수준의 향상된 결과를 나타내었다. BVH의 형상에 관계없이 1.5기압수준으로 약 30초 이상 동안 추출하면 BVH내부의 잔류기공은 제거 되어지며 JEDEC 기준의 신뢰성으로 평가한 결과 BVH내부에 잔류기공은 존재하지 않았다.

• Journal of Welding and Joining
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• 제16권5호
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• pp.100-107
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• 1998

This paper describes fluxless soldering of reflow soldering process using solder foil instead of solder pastes. There is an increasing demand for the reliable solder connection in the recent high density microelectronic components technologies. And also, it is problem fracture of an Ozone layer due to freon as which is used to removal of remained flux on the substrate. This paper discussed joining phenomena, boudability and joining processes of microelectronics devices, such as between outer lead of VLSI package and copper pad on a substrate without flux. The shear strength of joints is 8 to 13 N using Sn/Pb (63/37 wt.%) solder foil with optimum joining conditions, meanwhile, in case of using Sn/In (52/48 wt.%) solder foil, it is possible to bond with low heating temperature of 550 K, and accomplish to high bonding strength of 25N in condition heating temperature of 650K. Finally, this paper experimentally shows fluxless soldering using solder foil, and accomplishes key technology of microsoldering processes.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1990년도 하계학술대회 논문집
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• pp.211-214
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• 1990

The cordierite(2 MgO, $2Al_2O_3$, $5SiO_2$) is of great interest for microelectronic substrate of multilayer intergrated circuits. The metal used in this study was copper, and metal layer is fabricatedon the cordierite substrate by the screen printing method. We studied the adhesion properties of the interfaces due to the different cosintering conditions. When cosintering in the $Ar+H_2O$ gas, the adhesion is very good. Specially heating rate is very important factor for the adhesion.

• Korean Chemical Engineering Research
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• 제55권2호
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• pp.275-278
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• 2017

Heterogeneous semiconductor composites have been widely used to establish high-performance microelectronic or optoelectronic devices. During a deposition of silicon atoms on silicon/germanium compound surfaces, germanium (Ge) atoms are segregated from the substrate to the surface and are mixed in incoming a silicon layer. To suppress Ge segregation to obtain the interface sharpness between silicon layers and silicon/germanium composite layers, approaches have used silicon hydride gas species. The hydrogen atoms can play a role of inhibitors of silicon/germanium exchange. However, there are few kinetic models to explain the hydrogen effects. We propose using segregation probability which is affected by hydrogen atoms covering substrate surfaces. We derived the model to predict the segregation probability as well as the profile of Ge fraction through layers by using chemical reactions during silicon deposition.

• BMB Reports
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• 제38권5호
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• pp.517-525
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• 2005

Solid phase peptide synthesis method, which was introduced by Merrifield in 1963, has spawned the concept of combinatorial chemistry. In this review, we summarize the present technologies of solid phase peptide synthesis (SPPS) that are related to combinatorial chemistry. The conventional methods of peptide library synthesis on polymer support are parallel synthesis, split and mix synthesis and reagent mixture synthesis. Combining surface chemistry with the recent technology of microelectronic semiconductor fabrication system, the peptide microarray synthesis methods on a planar solid support are developed, which leads to spatially addressable peptide library. There are two kinds of peptide microarray synthesis methodologies: pre-synthesized peptide immobilization onto a glass or membrane substrate and in situ peptide synthesis by a photolithography or the SPOT method. This review also discusses the application of peptide libraries for high-throughput bioassays, for example, peptide ligand screening for antibody or cell signaling, enzyme substrate and inhibitor screening as well as other applications.

• 마이크로전자및패키징학회지
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• 제10권3호
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• pp.43-55
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• 2003

최근 IT산업의 발달과 그에 따른 전자부품기술의 발전이 가속화됨에 따라, 전자부품의 경박 단소화 및 고성능에 대한 요구는 전자패키지 (electronic package) 및 반도체기판(PKG substrate) 업체들로 하여금 고밀도의 입출력(I/O)과 우수한 열적, 전기적 특성을 보유하면서 높은 양산수율로 제품이 가격경쟁력을 갖도록 유도하고 있다. 이러한 경향에 따라 세계적인 반도체 회사(chip-maker)들은 더욱 혹독한 조건의 신뢰성 표준을 마련하여 제반 산업에 전반적인 적용을 요구하고 있으며, 환경친화 및 고주파, 고성능의 특성을 지닌 새로운 소재를 개발하도록 촉구하고 있는 실정이다. 반도체기판은 구성소재에 따라 구현되는 특성의 범위가 매우 크므로 우수한 특성의 소재를 반도체기판에 적용할 때 고객의 요구조건에 충분히 만족시킬 수 있을 것으로 기대된다. 따라서, 기판업계에서는 우수한 특성을 나타내는 원자재의 개발 및 수급이 절실하게 되었으며 급변하는 원자재의 기술 동향에 대한 분석은 향후 전자패키지 및 기판제품의 경쟁력을 향상시킬 수 있을 것이므로 본 연구에서는 최신 반도체기판 원자재의 기술 동향과 원자재의 특성을 분석하고자 하였다.

• 한국표면공학회지
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• 제35권4호
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• pp.218-231
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• 2002

As the environmental regulation worldwide emerges, most notably in Europe and Japan, the elimination of Pb usage in electronic assemblies has been an important issue for microelectronics assembly due to the inherent toxicity of Pb. This has provided an impetus towards the development of Pb-free solders. A major factor affecting alloy selection is the melting point, since this will have a major impact on the other polymeric materials used in microelectronic assembly and encapsulation. Other important manufacturing issues are cost, availability, and wetting characteristics. Reliability related properties include mechanical strength, fatigue resistance, coefficient of thermal expansion and reactivity with substrate. In this article, Pb-free solder alloys have been proposed so far have been reviewed and are summarized.

• Journal of information and communication convergence engineering
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• 제9권4호
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• pp.461-465
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• 2011

An aluminum doped zinc oxide (AZO) film for front contacts of thin film solar cells, in this work, were deposited by r.f. magnetron sputtering, and then etched in diluted hydrochloric acid solution for different times. Effects of surface texturing on the electro-optical properties of AZO films were investigated. Also, to clarify the light trapping of textured AZO film, amorphous silicon thin film solar cells were fabricated on the textured AZO/glass substrate and the performance of solar cells were studied. After texturing, the spectral haze at the visible range of 400 ~750 nm increased substantially with the etching time, without a change in the resistivity. The conversion efficiency of amorphous Si solar cells with textured AZO film as a front electrode was improved by the increase of short-circuit current density ($J_{sc}$), compared to cell with flat AZO films.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.259-259
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• 2008

The LTCC (Low Temperature Co-fired Ceramic) technology meets the requirements for high quality microelectronic devices and microsystems application due to a very good electrical and mechanical properties, high reliability and stability as well as possibility of making integrated three dimensional microstructures. The wet process, which has been applied to the etching of the metallic thin film on the ceramic substrate, has multi process steps such as lithography and development and uses very toxic chemicals arising the environmental problems. The other side, Plasma technology like ion beam sputtering is clean process including surface cleaning and treatment, sputtering and etching of semiconductor devices, and environmental cleanup. In this study, metallic multilayer pattern was fabricated by the ion beam etching of Ti/Pd/Cu without the lithography. In the experiment, Alumina and LTCC were used as the substrate and Ti/Pd/Cu metallic multilayer was deposited by the DC-magnetron sputtering system. After the formation of Cu/Ni/Au multilayer pattern made by the photolithography and electroplating process, the Ti/Pd/Cu multilayer was dry-etched by using the low energy-high current ion-beam etching process. Because the electroplated Au layer was the masking barrier of the etching of Ti/Pd/Cu multilayer, the additional lithography was not necessary for the etching process. Xenon ion beam which having the high sputtering yield was irradiated and was used with various ion energy and current. The metallic pattern after the etching was optically examined and analyzed. The rate and phenomenon of the etching on each metallic layer were investigated with the diverse process condition such as ion-beam acceleration energy, current density, and etching time.

• 마이크로전자및패키징학회지
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• 제23권3호
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• pp.63-67
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• 2016

본 논문에서는 폴리머 기반의 유연 기판 위 적층 된 다양한 필름의 굽힘 탄성계수의 간접 측정법을 소개한다. 패키징 기판의 다양한 적층 재료들의 탄성계수는 기계적으로 신뢰성 있는 전자기기 개발에 결정적이지만, 기판과 매우 견고히 접합하고 있는 적층 필름을 온전히 떼어 내어 자유지지형(free-standing) 시편을 만들기 어렵기 때문에 그 측정이 쉽지 않다. 이를 해결하기 위해 본 연구에서는 필름-기판의 복합체 시편에 대한 3점 굽힘을 진행하였고 시편 단면에 면적 변환법(area transformation rule)을 적용한 응력 해석을 수행하였다. 탄성계수를 알고 있는 기판에 대하여, 굽힘 시험으로 얻은 다층 시편의 강성으로부터 필름과 기판의 탄성계수 비를 계산하였으며, 전기 도금 구리 시편을 이용하여 양면 적층, 단면 적층의 두 가지 해석 모델이 실험 평가되었다. 또한 주요 절연체 적층 재료인 prepreg (PPG)와 dry film solder resist (DF SR)의 굽힘 탄성계수가 양면 적층 시편 형태로 측정 되었다. 결과로써 구리 110.3 GPa, PPG 22.3 GPa, DF SR 5.0 GPa이 낮은 측정 편차로 측정 됨으로써 본 측정법의 정밀도와 범용성을 검증하였다.