• 제목/요약/키워드: metal hole array

검색결과 25건 처리시간 0.022초

전계방출 및 근접 광센서 응용을 위한 서브 마이크론 aperture의 제작 (Microfabrication of submicron-size hole for potential held emission and near field optical sensor applications)

  • Lee, J.W.;Park, S.S.;Kim, J.W.;M.Y. Jung;Kim, D.W.
    • 한국진공학회지
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    • 제9권2호
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    • pp.99-101
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    • 2000
  • Submicron aperture 제작 기술은 near field optical sensor 또는 liquid metal ion source에 응용될 수 있는 가능성으로 인해 흥미를 모으고 있다. 본 실험에서는 submicron aperture 제작에 대해 기술할 것이다. 먼저 2 $\mu\textrm{m}$크기의 dot array를 광학 리소그라피 방법으로 패턴화하였다. KOH 비등방성 식각 방법으로 V-groove형을 만든 후, $1000^{\circ}C$에서 600분동안 건식 산화작업을 거쳤다. 이 산화과정에서 결정 방향에 따라 산화율이 달라지게 되는데 Si(111)면은 Si(100)면에 비해 산화율이 커서 두꺼운 산화막이 형성되며, 이 막은 연이은 건식식각 과정에서 etch-mask로 활용된다. Reactive ion etching은 ICP (Inductively Coupled Plasma) 장비를 사용하였으며, V-groove의 바닥에 형성된 90nm두께의 SiO$_2$와 그 아래의 Si을 식각하였다. 이 때, 기판에 걸린 negative bias는 $Cl_2$ RIE의 anisotropic etchig 효과를 증대시키는 것 같았으며, SEM촬영 결과 식각 후에 Si(111)면 위에는 약 130 nm정도의 산화층이 잔류하고 있었다. 이렇게 형성된 Si aperture는 향후 NSOM sensor등에 적용될 수 있을 것이다.

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Metal tip FEA 의 제조시 식각 용액이 게이트 산화막에 미치는 영향 (The effect of wet-etching process on the gate insulator for fabrication of metal tip FEA)

  • 정유호;정재호;박흥우;송만호;이윤희;주병권;오명환;김철주
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1996년도 하계학술대회 논문집 C
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    • pp.1450-1452
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    • 1996
  • In order to optimize the characteristics of gate insulator for FED(field emission device), we investigated the effect of wet-etching process on the gate insulator for fabrication of FED. We used the general three types of etchants for fabrication of the metal tip FEA(field emitter array), they are MO and oxide etchants to form the gate hole, and Al etchant to remove the release layer. In the result of the breakdown field of the insulator by the measure of the current-voltage characteristics, the breakdown field of insulator for immersing in oxide etchant was rapidly lowering with increasing etching time, but that for immersing in Al etchant was slow lowering. Also, in comparing cleaning with non-cleaning samples, the breakdown field of the cleaning samples was higher than that of non-cleaning samples.

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Trapped Field Analysis of a High Temperature Superconducting Bulk with Artificial Holes

  • Jang, Guneik;Lee, Man-Soo;Han, Seung-Yong;Kim, Chan-Joong;Han, Young-Hee;Park, Byung-Joon
    • Journal of Magnetics
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    • 제16권2호
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    • pp.181-185
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    • 2011
  • To improve trapped field characteristics of a high temperature superconducting (HTS) bulk, a technique to implement artificial holes has been studied. The artificial holes, filled up with epoxy or metal, may provide better cooling channel and enhance mechanical strength of the HTS bulk. Although many useful researches based on experiments have been reported, a numerical approach is still limited because of several reasons that include: 1) highly non-linear electromagnetic properties of HTS; and 2) difficulty in modeling of randomly scattered "small" artificial holes. In this paper, a 2-D finite element method with iteration is adopted to analyze trapped field characteristics of HTS bulk with artificial holes. The validity of the calculation is verified by comparison between measurement and calculation of a trapped field in a $40{\times}40\;mm$ square and 3.1 mm thick HTS bulk having 16 artificial holes with diameter of 0.7 mm. The effects of sizes and array patterns of artificial holes on distribution of trapped field within HTS bulk are numerically investigated using suggested method.

HgCdTe를 이용한 Infrared Detector의 제조와 특성 (Fabrication and Its Characteristics of HgCdTe Infrared Detector)

  • 김재묵;서상희;이희철;한석룡
    • 한국군사과학기술학회지
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    • 제1권1호
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    • pp.227-237
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    • 1998
  • HgCdTe Is the most versatile material for the developing infrared devices. Not like III-V compound semiconductors or silicon-based photo-detecting materials, HgCdTe has unique characteristics such as adjustable bandgap, very high electron mobility, and large difference between electron and hole mobilities. Many research groups have been interested in this material since early 70's, but mainly due to its thermodynamic difficulties for preparing materials, no single growth technique is appreciated as a standard growth technique in this research field. Solid state recrystallization(SSR), travelling heater method(THM), and Bridgman growth are major techniques used to grow bulk HgCdTe material. Materials with high quality and purity can be grown using these bulk growth techniques, however, due to the large separation between solidus and liquidus line on the phase diagram, it is very difficult to grow large materials with minimun defects. Various epitaxial growth techniques were adopted to get large area HgCdTe and among them liquid phase epitaxy(LPE), metal organic chemical vapor deposition(MOCVD), and molecular beam epitaxy(MBE) are most frequently used techniques. There are also various types of photo-detectors utilizing HgCdTe materials, and photovoltaic and photoconductive devices are most interested types of detectors up to these days. For the larger may detectors, photovoltaic devices have some advantages over power-requiring photoconductive devices. In this paper we reported the main results on the HgCdTe growing and characterization including LPE and MOCVD, device fabrication and its characteristics such as single element and linear array($8{\times}1$ PC, $128{\times}1$ PV and 4120{\times}1$ PC). Also we included the results of the dewar manufacturing, assembling, and optical and environmental test of the detectors.

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Microfabrication of Submicron-size Hole on the Silicon Substrate using ICP etching

  • Lee, J.W.;Kim, J.W.;Jung, M.Y.;Kim, D.W.;Park, S.S.
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 1999년도 제17회 학술발표회 논문개요집
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    • pp.79-79
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    • 1999
  • The varous techniques for fabrication of si or metal tip as a field emission electron source have been reported due to great potential capabilities of flat panel display application. In this report, 240nm thermal oxide was initially grown at the p-type (100) (5-25 ohm-cm) 4 inch Si wafer and 310nm Si3N4 thin layer was deposited using low pressure chemical vapor deposition technique(LPCVD). The 2 micron size dot array was photolithographically patterned. The KOH anisotropic etching of the silicon substrate was utilized to provide V-groove formation. After formation of the V-groove shape, dry oxidation at 100$0^{\circ}C$ for 600 minutes was followed. In this procedure, the orientation dependent oxide growth was performed to have a etch-mask for dry etching. The thicknesses of the grown oxides on the (111) surface and on the (100) etch stop surface were found to be ~330nm and ~90nm, respectively. The reactive ion etching by 100 watt, 9 mtorr, 40 sccm Cl2 feed gas using inductively coupled plasma (ICP) system was performed in order to etch ~90nm SiO layer on the bottom of the etch stop and to etch the Si layer on the bottom. The 300 watt RF power was connected to the substrate in order to supply ~(-500)eV. The negative ion energy would enhance the directional anisotropic etching of the Cl2 RIE. After etching, remaining thickness of the oxide on the (111) was measured to be ~130nm by scanning electron microscopy.

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