• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 추계학술대회 논문집 Vol.17
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• pp.53-56
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• 2004

This paper presents the improved burn-in method for the reliability of SRAM in MCP Semiconductor reliability is commonly improved through the burn-in process. Reliability problem is more significant in the Multi Chip Package, because of including over two devices in a package. In the SRAM-based Multi Chip Package, the failure of SRAM has a large effect on the yield and quality of the other chips - Flash Memory, DRAM, etc. So, the quality of SRAM must be guaranteed. To improve the quality of SRAM, we applied the improved wafer level burn-in process using multi cell selection method in addition to the current used methods. That method is effective in detecting special failure. Finally, with the composition of some kinds of methods, we could achieve the high qualify of SRAM in Multi Chip Package.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권6호
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• pp.662-667
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• 2013

The effect of fluorine ions, which can be reacted with boron in high-doped BPSG, is investigated on the contact sidewall wiggling profile in semiconductor process. In the semiconductor device, there are many contacts on $p^+/n^+$ source and drain region. However these types of wiggling profile is only observed at the $n^+$ contact region. As a result, we find that the type of plug implantation dopant can affect the sidewall wiggling profile of contact. By optimizing the proper fluorine gas flow rate, both the straight sidewall profile and the desired electrical characteristics can be obtained. In this paper, we propose a fundamental approach to improve the contact sidewall wiggling profile phenomena, which mostly appear in high-doped BPSG on next-generation DRAM products.

• 한국전기전자재료학회논문지
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• 제18권6호
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• pp.506-509
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• 2005

This paper presents the improved burn-in method for the reliability of SRAM in Multi Chip Package (MCP). Semiconductor reliability is commonly improved by the burn-in process. Reliability Problem is very significant in the MCP which includes over two chips in a package because the failure of one SRAM chip has a large influence on the yield and quality of the other chips such as Flash Memory, DRAM, etc. Therefore the quality of SRAM must be guaranteed. To improve the qualify of SRAM, we applied the improved wafer level burn-in process using multi cell selection method in addition to the previously used methods and it is found to be effective in detecting particular failures. Finally, with the composition of some kinds of methods, we achieved the high quality of SRAM in MCP.

• 한국분말재료학회지
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• 제1권2호
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• pp.145-152
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• 1994

Atomizing mode and powder characteristics of CuA1Ni base shape memory alloy in rotating disk atomization were investigated in accordance with disk materials and additional elements. Produced powders were classified into two types of spherical and flake shape. In the case of CuAlNiBTi and CuAlNiZr alloy, high yield rate and fine powder were obtained. This tendency was same when we used oxide coated disks. We concluded that this results were steno from the wetting characteristics change between molten metal and disk surface. Especially, due to the reactive properties of Ti and Zr with ceramic disk, the change of atomizing appearance and powder characteristics were noticeable.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 추계학술대회 논문집 전기물성,응용부문
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• pp.103-104
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• 2006

$Pb(Zr,Ti)O_3(PZT)$ is very attractive ferroelectric materials for ferroelectric random access memory (FeRAM) applications because of its high polarization ability and low process temperature. However, Chemical Mechanical Polishing (CMP) pressure and velocity must be carefully adjusted because FeRAM shrinks to high density devices. The contaminations such as slurry residues due to the absence of the exclusive cleaning chemicals are enough to influence on the degradation of PZT thin film capacitors. The surface characteristics of PZT thin film were investigated by the change of process parameters and the cleaning process. Both the low CMP pressure and the cleaning process must be employed, even if the removal rate and the yield were decreased, to reduce the fatigue of PZT thin film capacitors fabricated by damascene process. Like this, fatigue characteristics were partially controlled by the regulation of the CMP process parameters in PZT damascene process. And the exclusive cleaning chemicals for PZT thin films were developed in this work.

• 마이크로전자및패키징학회지
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• 제17권4호
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• pp.1-9
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• 2010

삼차원 집적화기술의 현황과 과제 및 향후에 요구되어질 새로운 삼차원 집적화기술의 필요성에 대해 논의를 하였다. Super-chip 기술이라 불리우는 자기조직화 웨이퍼집적화 기술 및 삼차원 헤테로집적화 기술에 대해 소개를 하였다. 액체의 표면장력을 이용하여지지 기반위에 다수의 KGD를 일괄 실장하는 새로운 집적화 기술을 적용하여, KGD만으로 구성된 자기조직화 웨이퍼를 다층으로 적층함으로써 크기가 다른 칩들을 적층하는 것에 성공을 하였다. 또한 삼차원 헤테로집적화 기술을 이용하여 CMOS LSI, MEMS 센서들의 전기소자들과 PD, VC-SEL등의 광학소자 및 micro-fluidic 등의 이종소자들을 삼차원으로 집적하여 시스템화하는데 성공하였다. 이러한 기술은 향후 TSV의 실용화 및 궁극의 3-D IC인 super-chip을 구현하는데 필요한 핵심기술이다.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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• pp.647-650
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• 2006

Low temperature polycrystalline silicon (LTPS) technology using a high power laser have been widely applied to thin film transistors (TFTs) for liquid crystal, organic light emitting diode (OLED) display, driver circuit for system on glass (SOG) and static random access memory (SRAM). Recently, the semiconductor industry is continuing its quest to create even more powerful CPU and memory chips. This requires increasing of individual device speed through the continual reduction of the minimum size of device features and increasing of device density on the chip. Moreover, the flat panel display industry also need to be brighter, with richer more vivid color, wider viewing angle, have faster video capability and be more durable at lower cost. Kornic Systems Co., Ltd. developed the $KORONA^{TM}$ LTP/GLTP series - an innovative production tool for fabricating flat panel displays and semiconductor devices - to meet these growing market demands and advance the volume production capabilities of flat panel displays and semiconductor industry. The $KORONA^{TM}\;LTP/GLTP$ series using DPSS laser and XeCl excimer laser is designed for the new generation of the wafer & FPD glass annealing processing equipment combining advanced low temperature poly-silicon (LTPS) crystallization technology and object-oriented software architecture with a semistandard graphical user interface (GUI). These leading edge systems show the superior annealing ability to the conventional other method. The $KORONA^{TM}\;LTP/GLTP$ series provides technical and economical benefits of advanced annealing solution to semiconductor and FPD production performance with an exceptional level of productivity. High throughput, low cost of ownership and optimized system efficiency brings the highest yield and lowest cost per wafer/glass on the annealing market.

• 한국콘텐츠학회논문지
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• 제18권11호
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• pp.527-539
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• 2018

노화로 인한 인지의 변화는 정상 노인들의 통사처리에 부정적 영향을 끼치는데 작업기억용량이 중요한 인지기능을 한다고 알려져 있다. 본 연구는 명사구 연결 전치사구의 이해에 도움이 되는 문맥을 제시할 때와 그렇지 않을 때 정상 노인과 젊은 성인이 어떻게 명사구 연결 전치사구를 처리하는지 단어별 자율조절읽기 방법을 통해 알아보았다. 또한, 이 때 어떤 인지기능이 문맥 이용을 통한 명사구 연결 전치사구의 처리능력과 관련이 있는지도 살펴보았다. 정상 노인은 읽기과제에서 문맥유무에 상관없이 젊은 성인보다 읽기속도가 느렸다. 그러나 두 그룹 모두 문맥이 존재할 때 명사구 연결 전치사구의 처리 속도가 빨랐다. 즉, 노인들의 노화로 인한 인지의 저하는 처리 속도만 느리게 했을 뿐 질적인 면에서 차이는 없었다. 문맥을 이용한 명사구 연결 전치사구 처리 시 관련된 인지기능은 교대주의력으로 나타났으며 본 연구에서는 작업기억용량의 역할은 발견되지 않았다. 이를 통해 노화가 통사처리에 끼치는 영향은 반드시 부정적인 것이 아니라 통사구조에 따라 다를 수 있으며, 통사 구문의 종류에 따라 관련된 인지기능이 다를 수 있음을 시사한다.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2002년도 춘계학술대회 논문집
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• pp.348-352
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• 2002

a basis such as IT(Information Technology), NT(Nano Technology) and BT(Bio Technology). Recently, NT is applied to various fields that are composed of science, industry, media and semiconductor-micro technology. It has need of IT that is ultra-precision positioning technology with strokes of many hundreds mm and maintenance of nm precision in fields of ultra micro process, ultra precision measurement, photo communication part and photo magnetic memory. This thesis represents optimal design on ultra-precision positioning with single plane X-Y stage and development of artificial control system for adequacy of industrial demand. Also, dynamic simulation on global stage is performed by using ADAMS (Automated Dynamic Analysis of Mechanical System) for the purpose of grasping dynamic characteristic on user designed X-Y global stage. The error between displacements from micro stage and from FEM(Finite Element Method) is 3.53% by verifications of stability on micro stage and control performance. As maximum Von-mises stress on hinge of micro stage is 5.981kg/mm$^2$ that is 1.5% of yield stress, stability on hinge is secured. Preparing previous results, optimal design of micro stage can be possible, and reliance of results with FEM can be secured.

• 대한전자공학회논문지SD
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• 제41권5호
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• pp.51-60
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• 2004

반도체 기술의 발달로 회로의 집적도와 복잡도가 증가함에 따라 칩의 생산 과정에서 고장이 발생하는 빈도가 높아지게 되었다. 칩의 수율을 향상시키고, 생산 단가를 절감시키기 위해서 고장의 원인을 찾아내고 분석하는 과정은 매우 중요하다. 그러나 고장의 원인을 분석하는 과정 중 고장의 위치를 찾아내는 데는 많은 시간이 소요된다. 게이트 수준에서의 고장 위치 진단은 물리적 수준에서의 고장 범위를 한정해 줌으로써 고장 위치를 찾는 데 소요되는 시간을 줄 일 수 있다는 데 의미를 갖는다. 본 논문에서는 새로운 방식의 고장 딕션너리 방식과 추가적인 고장 시뮬레이션 방식을 혼합하여, 메모리의 소비를 최소화하면서도 시뮬레이션 수행 시간을 단축시킴으로써 효과적으로 고장 진단을 수행할 수 있는 고장 진단 알고리듬을 제안한다.