• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.53-56
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• 2004

This paper presents the improved burn-in method for the reliability of SRAM in MCP Semiconductor reliability is commonly improved through the burn-in process. Reliability problem is more significant in the Multi Chip Package, because of including over two devices in a package. In the SRAM-based Multi Chip Package, the failure of SRAM has a large effect on the yield and quality of the other chips - Flash Memory, DRAM, etc. So, the quality of SRAM must be guaranteed. To improve the quality of SRAM, we applied the improved wafer level burn-in process using multi cell selection method in addition to the current used methods. That method is effective in detecting special failure. Finally, with the composition of some kinds of methods, we could achieve the high qualify of SRAM in Multi Chip Package.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.6
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• pp.662-667
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• 2013

The effect of fluorine ions, which can be reacted with boron in high-doped BPSG, is investigated on the contact sidewall wiggling profile in semiconductor process. In the semiconductor device, there are many contacts on $p^+/n^+$ source and drain region. However these types of wiggling profile is only observed at the $n^+$ contact region. As a result, we find that the type of plug implantation dopant can affect the sidewall wiggling profile of contact. By optimizing the proper fluorine gas flow rate, both the straight sidewall profile and the desired electrical characteristics can be obtained. In this paper, we propose a fundamental approach to improve the contact sidewall wiggling profile phenomena, which mostly appear in high-doped BPSG on next-generation DRAM products.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.6
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• pp.506-509
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• 2005

This paper presents the improved burn-in method for the reliability of SRAM in Multi Chip Package (MCP). Semiconductor reliability is commonly improved by the burn-in process. Reliability Problem is very significant in the MCP which includes over two chips in a package because the failure of one SRAM chip has a large influence on the yield and quality of the other chips such as Flash Memory, DRAM, etc. Therefore the quality of SRAM must be guaranteed. To improve the qualify of SRAM, we applied the improved wafer level burn-in process using multi cell selection method in addition to the previously used methods and it is found to be effective in detecting particular failures. Finally, with the composition of some kinds of methods, we achieved the high quality of SRAM in MCP.

• Journal of Powder Materials
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• v.1 no.2
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• pp.145-152
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• 1994

Atomizing mode and powder characteristics of CuA1Ni base shape memory alloy in rotating disk atomization were investigated in accordance with disk materials and additional elements. Produced powders were classified into two types of spherical and flake shape. In the case of CuAlNiBTi and CuAlNiZr alloy, high yield rate and fine powder were obtained. This tendency was same when we used oxide coated disks. We concluded that this results were steno from the wetting characteristics change between molten metal and disk surface. Especially, due to the reactive properties of Ti and Zr with ceramic disk, the change of atomizing appearance and powder characteristics were noticeable.

• Proceedings of the KIEE Conference
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• 2006.10a
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• pp.103-104
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• 2006

$Pb(Zr,Ti)O_3(PZT)$ is very attractive ferroelectric materials for ferroelectric random access memory (FeRAM) applications because of its high polarization ability and low process temperature. However, Chemical Mechanical Polishing (CMP) pressure and velocity must be carefully adjusted because FeRAM shrinks to high density devices. The contaminations such as slurry residues due to the absence of the exclusive cleaning chemicals are enough to influence on the degradation of PZT thin film capacitors. The surface characteristics of PZT thin film were investigated by the change of process parameters and the cleaning process. Both the low CMP pressure and the cleaning process must be employed, even if the removal rate and the yield were decreased, to reduce the fatigue of PZT thin film capacitors fabricated by damascene process. Like this, fatigue characteristics were partially controlled by the regulation of the CMP process parameters in PZT damascene process. And the exclusive cleaning chemicals for PZT thin films were developed in this work.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.4
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• pp.1-9
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• 2010

Three-dimensional (3-D) integration is an emerging technology, which vertically stacks and interconnects multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked chip to form highly integrated micro-nano systems. Since CMOS device scaling has stalled, 3D integration technology allows extending Moore's law to ever high density, higher functionality, higher performance, and more diversed materials and devices to be integrated with lower cost. The potential benefits of 3D integration can vary depending on approach; increased multifunctionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, increased yield and reliability, flexible heterogeneous integration, and reduced overall costs. It is expected that the semiconductor industry's paradiam will be shift to a new industry-fusing technology era that will offer tremendous global opportunities for expanded use of 3D based technologies in highly integrated systems. Anticipated applications start with memory, handheld devices, and high-performance computers and extend to high-density multifunctional heterogeneous integration of IT-NT-BT systems. This paper attempts to introduce new 3D integration technologies of the chip self-assembling stacking and 3D heterogeneous opto-electronics integration for realizng the super-chip.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.647-650
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• 2006

Low temperature polycrystalline silicon (LTPS) technology using a high power laser have been widely applied to thin film transistors (TFTs) for liquid crystal, organic light emitting diode (OLED) display, driver circuit for system on glass (SOG) and static random access memory (SRAM). Recently, the semiconductor industry is continuing its quest to create even more powerful CPU and memory chips. This requires increasing of individual device speed through the continual reduction of the minimum size of device features and increasing of device density on the chip. Moreover, the flat panel display industry also need to be brighter, with richer more vivid color, wider viewing angle, have faster video capability and be more durable at lower cost. Kornic Systems Co., Ltd. developed the $KORONA^{TM}$ LTP/GLTP series - an innovative production tool for fabricating flat panel displays and semiconductor devices - to meet these growing market demands and advance the volume production capabilities of flat panel displays and semiconductor industry. The $KORONA^{TM}\;LTP/GLTP$ series using DPSS laser and XeCl excimer laser is designed for the new generation of the wafer & FPD glass annealing processing equipment combining advanced low temperature poly-silicon (LTPS) crystallization technology and object-oriented software architecture with a semistandard graphical user interface (GUI). These leading edge systems show the superior annealing ability to the conventional other method. The $KORONA^{TM}\;LTP/GLTP$ series provides technical and economical benefits of advanced annealing solution to semiconductor and FPD production performance with an exceptional level of productivity. High throughput, low cost of ownership and optimized system efficiency brings the highest yield and lowest cost per wafer/glass on the annealing market.

• The Journal of the Korea Contents Association
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• v.18 no.11
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• pp.527-539
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• 2018

Cognitive decline in aging is known to yield detrimental effects in syntactic processing and working memory capacity is the most crucial cognitive function in understanding older adults' sentence processing skills. This study examined how young and older adults utilize contextual information while resolving NP-attached Ps vis word-by-word self-paced reading paradigm. In addition, the study asked which cognitive functions play roles on the use of a NP-supporting context during processing of NP-attached PP. When NP-attached PP was presented in a supporting context, both age groups performed faster than in the null context condition. Among different cognitive functions, alternating attention skills were correlated with the ability utilizing context during syntactic ambiguity resolution and working memory capacity was not found to be crucial for this study. In conclusion, this study suggests that aging does not always affect older adults' syntactic processing negatively and relevant cognitive function may vary depending on the type of syntactic structure.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2002.05a
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• pp.348-352
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• 2002

a basis such as IT(Information Technology), NT(Nano Technology) and BT(Bio Technology). Recently, NT is applied to various fields that are composed of science, industry, media and semiconductor-micro technology. It has need of IT that is ultra-precision positioning technology with strokes of many hundreds mm and maintenance of nm precision in fields of ultra micro process, ultra precision measurement, photo communication part and photo magnetic memory. This thesis represents optimal design on ultra-precision positioning with single plane X-Y stage and development of artificial control system for adequacy of industrial demand. Also, dynamic simulation on global stage is performed by using ADAMS (Automated Dynamic Analysis of Mechanical System) for the purpose of grasping dynamic characteristic on user designed X-Y global stage. The error between displacements from micro stage and from FEM(Finite Element Method) is 3.53% by verifications of stability on micro stage and control performance. As maximum Von-mises stress on hinge of micro stage is 5.981kg/mm$^2$ that is 1.5% of yield stress, stability on hinge is secured. Preparing previous results, optimal design of micro stage can be possible, and reliance of results with FEM can be secured.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.5
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• pp.51-60
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• 2004

Due to the improvements in circuit design and manufacturing technique, the complexity of a circuit is growing. Since the complexity of a circuit causes high frequency of faults, it is very important to locate faults for improvement of yield and reduction of production cost. But unfortunately it takes a long time to find sites of defects by e-beam proving if the physical level. A fault diagnosis algorithm in the Sate level has meaning to reduce diagnosis time by limiting fault sites. In this paper, we propose an efficient fault diagnosis algorithm in the logical level. Our method is hybrid fault diagnosis algorithm using a new fault dictionary and additional fault simulation which minimizes memory consumption and simulation time.