• 제목/요약/키워드: memory testing

검색결과 244건 처리시간 0.023초

Social Isolation Selectively Increases Anxiety in Mice without Affecting Depression-like Behavior

  • Kwak, Chul-Jung;Lee, Sue-Hyun;Kaang, Bong-Kiun
    • The Korean Journal of Physiology and Pharmacology
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    • 제13권5호
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    • pp.357-360
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    • 2009
  • It is hypothesized that a number of environmental factors affect animals' behavior. Without controlling these variables, it is very hard for researchers to get not only reliable, but replicable data from various behavioral experiments testing animals' cognitive as well as emotional functions. For example, laboratory mice which had restricted environment showed different synaptic potentiation properties with wild mice (Zhao MG et al., 2009). While performing behavioral experiments, however, it is sometimes inevitable that the researcher changes the animals' environments, as by switching the cages in which experimental animals are housed and separating animals raised together into small experimental groups. In this study, we investigated the effect of environmental changes on mice's emotional behaviors by socially isolating them or reducing the size of their cage. We found that social isolation selectively increases the animals' levels of anxiety, while leaving depression-like behaviors unchanged. On the other hand, alteration of the housing dimensions affected neither their anxiety levels nor their depression-like behaviors. These results suggest that environmental variables may have a prominent impact on experimental animals' emotional behaviors and possibly their psychological states, leading to bias in the behavioral data produced from experiments.

Distributed crack sensors featuring unique memory capability for post-earthquake condition assessment of RC structures

  • Chen, Genda;McDaniel, Ryan;Sun, Shishuang;Pommerenke, David;Drewniak, James
    • Smart Structures and Systems
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    • 제1권2호
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    • pp.141-158
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    • 2005
  • A new design of distributed crack sensors based on the topological change of transmission line cables is presented for the condition assessment of reinforced concrete (RC) structures during and immediately after an earthquake event. This study is primarily focused on the performance of cable sensors under dynamic loading, particularly a feature that allows for some "memory" of the crack history of an RC member. This feature enables the post-earthquake condition assessment of structural members such as RC columns, in which the earthquake-induced cracks are closed immediately after an earthquake event due to gravity loads, and are visually undetectable. Factors affecting the onset of the feature were investigated experimentally with small-scale RC beams under cyclic loading. Test results indicated that both crack width and the number of loading cycles were instrumental in the onset of the memory feature of cable sensors. Practical issues related to dynamic acquisition with the sensors are discussed. The sensors were proven to be fatigue resistant from shake table tests of RC columns. The sensors continued to show useful performance after the columns can no longer support additional loads.

MCU에 내장된 플레쉬 메모리 오동작 테스트 가능한 ROM Writer 개발 (Development of a ROM Writer for Shmoo Test of a Flash Memory Integrated into the MCU)

  • 김태선;박차훈
    • 한국산업정보학회논문지
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    • 제20권4호
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    • pp.103-109
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    • 2015
  • 본 논문은 MCU에 내장된 플레쉬 메모리의 오동작 테스트를 shmoo 테스트 기법을 사용하고, 이 기능을 내장한 롬라이트 개발에 관한 논문이다. shmoo 테스트는 다양한 입력조건에 대한 응답을 도표로 나타내고 분석하는 기법으로, 마이크로프로세서, ASIC 및 메모리와 같은 집적회로 또는 컴퓨터 시스템의 성능분석의 기법으로 사용된다. 개발된 롬라이터는 Shmoo 검사를 수행하고 Flash 32K의 쓰기를 수행하였을 때 6.4s 정도의 시간이 소요되었으며, 이는 현재 사용하고 있는 ROM Writer의 속도에 비해 약 20% 정도 향상되었다.

채우기 밀도별 형상 기억 TPU 3D 프린팅 Re-entrant 스트립의 특성 분석 (Characterization of 3D Printed Re-entrant Strips Using Shape Memory Thermoplastic Polyurethane with Various Infill Density)

  • 정임주;이선희
    • 한국의류산업학회지
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    • 제24권6호
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    • pp.812-824
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    • 2022
  • This study proposes to develop a 3D printed re-entrant(RE) strip by shape memory thermoplastic polyurethane that can be deformed and recovered by thermal stimulation. The most suitable 3D printing infill density condition and temperature condition during shape recovery for mechanical behavior were confirmed. As the poisson's ratio indicated, the higher the recovery temperature, the closer the poisson's ratio to zero and the better the auxetic properties. After recovery testing for five minutes, it appeared that the shape recovery ratio was the highest at 70℃. The temperature range when the shape recovery ratio appeared to be more than 90% was a recovery temperature of more than 50℃ and 60℃ when deformed under a constant load of 100 gf and 300 gf, respectively. This indicated that further deformation occurred after maximum recovery when recovered at a temperature of 80℃, which is above the glass transition temperature range. As for REstrip by infill density, a shape recovery properties of 100% was superior than 50%. Additionally, as the re-entrant structure exhibited a shape recovery ratio of more than 90%, and exhibited auxetic properties. It was confirmed that the infill density condition of 100% and the temperature condition of 70℃ are suitable for REstrips for applying the actuator.

형상기억합금을 이용한 슬릿댐퍼 적용 역V형 편심가새골조의 내진 성능 (Seismic Performance of an Inverted V-type Eccentrically Braced Steel Frames with Slit Dampers Using Shape Memory Alloy)

  • 장한렬;김주우
    • 한국공간구조학회논문집
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    • 제22권4호
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    • pp.39-48
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    • 2022
  • The energy dissipation of inverted V-type eccentric steel braced frames can be achieved through the yielding of a slit link, through yielding of a number of strips between slits when the frame is subjected to inelastic cyclic deformation. On the other hand, the development of seismic resistance system without residual deformation is obtained by applying the superelasdtic shape memory alloy (SMA) material into the brace and link elements. This paper presents results from a systematic three-dimensional nonlinear finite element analysis on the structural behavior of the eccentric bracing systems subjected to cyclic loadings. A wide scope of structural behaviors explains the horizontal stiffness, hysteretic behaviors, and failure modes of the recentering eccentric bracing system. The accurate results presented here serve as benchmark data for comparison with results obtained using modern experimental testing and alternative theoretical approaches.

철계 형상기억합금을 이용한 콘크리트 기둥의 전단보강 실험연구 (Experimental Study on Shear Retrofitting of Concrete Columns Using Iron-Based Shape Memory Alloy)

  • 정동혁;정새벽;최재희;김근오
    • 한국지진공학회논문집
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    • 제28권1호
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    • pp.41-46
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    • 2024
  • The current study investigates the seismic performance of shear-dominant RC columns retrofitted with iron-based shape memory alloy (Fe SMA). Three RC columns with insufficient transverse reinforcement were designed and fabricated for lateral cyclic loading tests. Before testing, two specimens were externally confined with carbon fiber-reinforced polymer (CFRP) sheets and self-prestressed Fe SMA strips. The test results showed that both CFRP and Fe SMA performed well in preventing severe shear failure exhibited by the unretrofitted control specimen. Furthermore, the two retrofitted specimens showed ductile flexural responses up to the drift ratios of ±8%. In terms of damage control, however, the Fe SMA confinement was superior to CFRP confinement in that the spalling of concrete was much less and that the rupture of confinement did not occur.

A Study on the Built-In Self-Test for AC Parameter Testing of SDRAM using Image Graphic Controller

  • Park, Sang-Bong;Park, Nho-Kyung;Kim, Sang-Hun
    • The Journal of the Acoustical Society of Korea
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    • 제20권1E호
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    • pp.14-19
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    • 2001
  • We have proposed BIST method and circuit for embedded 16M SDRAM with logic. It can test the AC parameter of embedded 16M SDRAM using the BIST circuit capable of detecting the address of a fail cell installed in an Merged Memory with Logic(MML). It generates the information of repair for redundancy circuit. The function and AC parameter of the embedded memory can also be tested using the proposed BIST method. It is possible to test the embedded SDRAM without external test pin. The total gate of the BIST circuit is approximately 4,500 in the case of synthesizing by 0.25μm cell library and is verified by Verilog simulation. The test time of each one AC parameter is about 200ms using 2Y-March 14n algorithm.

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Design and testing of a minimally invasive intervertebral cage for spinal fusion surgery

  • Anderson, Walter;Chapman, Cory;Karbaschi, Zohreh;Elahinia, Mohammad;Goel, Vijay
    • Smart Structures and Systems
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    • 제11권3호
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    • pp.283-297
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    • 2013
  • An innovative cage for spinal fusion surgery is presented within this work. The cage utilizes shape memory alloy for its hinge actuation. Because of the use of SMA, a smaller incision is needed which makes the cage deployment minimally invasive. In the development of the cage, a model for predicting the torsional behavior of SMAs was developed and verified experimentally. The prototype design of the cage was developed and manufactured. The prototype was subjected to static tests per ASTM specifications. The cage survived all of the tests, alluding to its safety within the body.

LED 전광판 제어 ASIC 의 설계 (A design of LED pannel control ASCI)

  • 이수범;남상길;조경연;김종진
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 1998년도 하계종합학술대회논문집
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    • pp.839-842
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    • 1998
  • The wide spread of multimedia system demands a large viewin gdesply device which can inform a message to many peoples in open area. This paper is about the design, simulating and testing of a large viewing LED pannel control ASIC(application specific integrated circuit). This LED pannel control ASIC runs on 16 bit microprocessor MC68EC000 and has following functions:16 line interlaced LED pannel controller, memory controller, 16 channel priority inerrupt controller, 2 channel direct memory access controller, 2 channel 12 bit clock and timer, 2 channel infrared remocon receiver, 2 channel RS-232C with 16byte FIFO, IBM PC/AT compatible keyboard interface, battery backuped real time clock, ISA bus controller, battery backuped 256 byte SRAM and watech dog timer. The 0.6micron CMOS sea of gate is used to design the ASIC in amount of about 39,000 gates.

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병렬구조 컴퓨터에서 Branch penalty를 감소시키기 위한 소프트웨어와 하드웨어 방법 (A Software And Hardware Scheme For Reducing The Branch Penalty In Parallel Computers)

  • 함찬숙;조종현;조영일
    • 전자공학회논문지B
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    • 제30B권11호
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    • pp.11-16
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    • 1993
  • VLIW architecture capable of testing multiple conditions in a cycle must support an efficient mechanism for multi-way branches. This paper proposes a mechanism to speed up the execution of multi-way branches and an efficient memory packing method of instructions, which reduced the wasted memory space. Also, we develops a new compiler technique which can transform program segments that are not applied to multi-way branches into ones that are applied to multi-way branches. The benefits gained by the transformation are to reduce branch penalty and to increase instruction-level parallelism.

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