• 제목/요약/키워드: memory stacking

검색결과 26건 처리시간 0.02초

Ultimate Heterogeneous Integration Technology for Super-Chip (슈퍼 칩 구현을 위한 헤테로집적화 기술)

  • Lee, Kang-Wook
    • Journal of the Microelectronics and Packaging Society
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    • 제17권4호
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    • pp.1-9
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    • 2010
  • Three-dimensional (3-D) integration is an emerging technology, which vertically stacks and interconnects multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked chip to form highly integrated micro-nano systems. Since CMOS device scaling has stalled, 3D integration technology allows extending Moore's law to ever high density, higher functionality, higher performance, and more diversed materials and devices to be integrated with lower cost. The potential benefits of 3D integration can vary depending on approach; increased multifunctionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, increased yield and reliability, flexible heterogeneous integration, and reduced overall costs. It is expected that the semiconductor industry's paradiam will be shift to a new industry-fusing technology era that will offer tremendous global opportunities for expanded use of 3D based technologies in highly integrated systems. Anticipated applications start with memory, handheld devices, and high-performance computers and extend to high-density multifunctional heterogeneous integration of IT-NT-BT systems. This paper attempts to introduce new 3D integration technologies of the chip self-assembling stacking and 3D heterogeneous opto-electronics integration for realizng the super-chip.

3-D Hetero-Integration Technologies for Multifunctional Convergence Systems

  • Lee, Kang-Wook
    • Journal of the Microelectronics and Packaging Society
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    • 제22권2호
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    • pp.11-19
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    • 2015
  • Since CMOS device scaling has stalled, three-dimensional (3-D) integration allows extending Moore's law to ever high density, higher functionality, higher performance, and more diversed materials and devices to be integrated with lower cost. 3-D integration has many benefits such as increased multi-functionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, because it vertically stacks multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked chip. Anticipated applications start with memory, handheld devices, and high-performance computers and especially extend to multifunctional convengence systems such as cloud networking for internet of things, exascale computing for big data server, electrical vehicle system for future automotive, radioactivity safety system, energy harvesting system and, wireless implantable medical system by flexible heterogeneous integrations involving CMOS, MEMS, sensors and photonic circuits. However, heterogeneous integration of different functional devices has many technical challenges owing to various types of size, thickness, and substrate of different functional devices, because they were fabricated by different technologies. This paper describes new 3-D heterogeneous integration technologies of chip self-assembling stacking and 3-D heterogeneous opto-electronics integration, backside TSV fabrication developed by Tohoku University for multifunctional convergence systems. The paper introduce a high speed sensing, highly parallel processing image sensor system comprising a 3-D stacked image sensor with extremely fast signal sensing and processing speed and a 3-D stacked microprocessor with a self-test and self-repair function for autonomous driving assist fabricated by 3-D heterogeneous integration technologies.

Characterization of a TSV sputtering equipment by numerical modeling (수치 모델을 이용한 TSV 스퍼터링 장비의 특성 해석)

  • Ju, Jeong-Hun
    • Proceedings of the Korean Institute of Surface Engineering Conference
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    • 한국표면공학회 2018년도 춘계학술대회 논문집
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    • pp.46-46
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    • 2018
  • 메모리 소자의 수요가 데스크톱 컴퓨터의 정체와 모바일 기기의 폭발적인 증가로 NAND flash 메모리의 고집적화로 이어져서 3차원 집적 기술의 고도화가 중요한 요소가 되고 있다. 1 mm 정도의 얇은 웨이퍼 상에 만들어지는 메모리 소자는 실제 두께는 몇 마이크로미터 되지 않는다. 수직방향으로 여러 장의 웨이퍼를 연결하면 폭 방향으로 이미 거의 한계에 도달해있는 크기 축소(shrinking) 기술에 의지 하지 않고서도 메모리 소자의 용량을 증대 시킬 수 있다. CPU, AP등의 논리 연산 소자의 경우에는 발열 문제로 3D stacking 기술의 구현이 쉽지 않지만 메모리 소자의 경우에는 저 전력화를 통해서 실용화가 시작되었다. 스마트폰, 휴대용 보조 저장 매체(USB memory, SSD)등에 수 십 GB의 용량이 보편적인 현재, FEOL, BEOL 기술을 모두 가지고 있는 국내의 반도체 소자 업체들은 자연스럽게 TSV 기술과 이에 필요한 장비의 개발에 관심을 가지게 되었다. 특히 이 중 TSV용 스퍼터링 장치는 transistor의 main contact 공정에 전 세계 시장의 90% 이상을 점유하고 있는 글로벌 업체의 경우에도 완전히 만족스러운 장비를 공급하지는 못하고 있는 상태여서 연구 개발의 적절한 시기이다. 기본 개념은 일반적인 마그네트론 스퍼터링이 중성 입자를 타겟 표면에서 발생시키는데 이를 다시 추가적인 전력 공급으로 전자 - 중성 충돌로 인한 이온화 과정을 추가하고 여기서 발생된 타겟 이온들을 웨이퍼의 표면에 최대한 수직 방향으로 입사시키려는 노력이 핵심이다. 본 발표에서는 고전력 이온화 스퍼터링 시스템의 자기장 해석, 냉각 효율 해석, 멀티 모듈 회전 자석 음극에 대한 동역학적 분석 결과를 발표한다. 그림1에는 이중 회전 모듈에 대한 다물체 동역학 해석을 Adams s/w package로 해석하기 위하여 작성한 모델이고 그림2는 180도 회전한 서브 모듈의 위상이 음극 냉각에 미치는 효과를 CFD-ACE+로 유동 해석한 결과를 나타내고 있다.

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Ground State Computation of Interacting Fermion Systems by using Advanced Stochastic Diagonalization (진보된 혼돈 대각화 방법을 이용한 상호작용하는 페르미온 계의 기저상태 계산)

  • Ahn, Sul-Ah;Cho, Myoung Won
    • Proceedings of the Korea Contents Association Conference
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    • 한국콘텐츠학회 2007년도 추계 종합학술대회 논문집
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    • pp.209-211
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    • 2007
  • The computational time of Stocahstic Diagonalization (SD) calculation for 2-dimensional interacting fermion systems is reduced by using several methods including symmetry operations. First, each lattice is subdivided into spin-up and spin-down lattices separately, thus allowing a bi-partite lattice. A valid basis state is then obtained from stacking up an up-spin configuration on top of a down-spin configuration. As a consequence, the memory space to be used in saving the trial basis state reduces significantly. Secondly, the matrix elements of a Hamiltonianin are reconrded in a look-up table when making basis state set. Thus the repeated calculation of the matrix elements of the Hamiltonian are avoided during SD process. Thirdly, by applying symmetry operations to the basis state set the original basis state is transformed to a new basis state whose elements are the eigenvectors of the symmetry operations. The ground state wavefunction is constructed from the elements of symmetric - bonding state - basis state set. As a result, the total number of basis states involved in SD calculation is reduced upto 50 percentage by using symmetry operations.

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Trend and Prospect for 3Dimensional Integrated-Circuit Semiconductor Chip (3차원 집적회로 반도체 칩 기술에 대한 경향과 전망)

  • Kwon, Yongchai
    • Korean Chemical Engineering Research
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    • 제47권1호
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    • pp.1-10
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    • 2009
  • As a demand for the portable device requiring smaller size and better performance is in hike, reducing the size of conventionally used planar 2 dimensional chip cannot be a solution for the enhancement of the semiconductor chip technology due to an increase in RC delay among interconnects. To address this problem, a new technology - "3 dimensional (3D) IC chip stack" - has been emerging. For the integration of the technology, several new key unit processes (e.g., silicon through via, wafer thinning and wafer alignment and bonding) should be developed and much effort is being made to achieve the goal. As a result of such efforts, 4 and 8 chip-stacked DRAM and NAND structures and a system stacking CPU and memory chips vertically were successfully developed. In this article, basic theory, configurations and key unit processes for the 3D IC chip integration, and a current tendency of the technology are explained. Future opportunities and directions are also discussed.

Application of KOMPSAT-5 SAR Interferometry by using SNAP Software (SNAP 소프트웨어를 이용한 KOMPSAT-5 SAR 간섭기법 구현)

  • Lee, Hoonyol
    • Korean Journal of Remote Sensing
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    • 제33권6_3호
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    • pp.1215-1221
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    • 2017
  • SeNtinel's Application Platform (SNAP) is an open source software developed by the European Space Agency and consists of several toolboxes that process data from Sentinel satellite series, including SAR (Synthetic Aperture Radar) and optical satellites. Among them, S1TBX (Sentinel-1 ToolBoX)is mainly used to process Sentinel-1A/BSAR images and interferometric techniques. It provides flowchart processing method such as Graph Builder, and has convenient functions including automatic downloading of DEM (Digital Elevation Model) and image mosaicking. Therefore, if computer memory is sufficient, InSAR (Interferometric SAR) and DInSAR (Differential InSAR) perform smoothly and are widely used recently in the world through rapid upgrades. S1TBX also includes existing SAR data processing functions, and since version 5, the processing capability of KOMPSAT-5 has been added. This paper shows an example of processing the interference technique of KOMPSAT-5 SAR image using S1TBX of SNAP. In the open mine of Tavan Tolgoi in Mongolia, the difference between DEM obtained in KOMPSAT-5 in 2015 and SRTM 1sec DEM obtained in 2000 was analyzed. It was found that the maximum depth of 130 meters was excavated and the height of the accumulated ore is over 70 meters during 15 years. Tidal and topographic InSAR signals were observed in the glacier area near Jangbogo Antarctic Research Station, but SNAP was not able to treat it due to orbit error and DEM error. In addition, several DInSAR images were made in the Iraqi desert region, but many lines appearing in systematic errors were found on coherence images. Stacking for StaMPS application was not possible due to orbit error or program bug. It is expected that SNAP can resolve the problem owing to a surge in users and a very fast upgrade of the software.