• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.360-363
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• 1999

Video data compression is a major key technology in the field of multimedia applications. Variable-length coding is the most popular data compression technique which has been used in many data compression standards, such as JPEG, MPEG and image data compression standards, etc. In this paper, we present memory efficient VLC decoder architecture for MPEG-2 application which can achieve small memory space and higher throughput. To reduce the memory size, we propose a new grouping, remainder generation method and merged lookup table (LUT) for variable length decoders (VLD's). In the MPEG-2, the discrete cosine transform (DCT) coefficient table zero and one are mapped onto one memory whose space requirement has been minimized by using efficient memory mapping strategy The proposed memory size is only 256 words in spite of mapping two DCT coefficient tables.

• Journal of the Korea Convergence Society
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• v.12 no.12
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• pp.365-370
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• 2021

The current study aims to investigate the relationship between working memory capacity, vocabulary size, and listening competence of Korean EFL (English as a Foreign Language) learners. 30 English education majors from a university in Korea were recruited. The backward digit span and the operation span tasks were used to measure the participants' working memory capacity, while the Listening Vocabulary Level Test (LVLT) and the Michigan English Test (MET) were employed to measure their vocabulary size and listening proficiency in English, respectively. The correlational analyses revealed that the bigger one's working memory storage was, the better the person processed incoming input. However, no statistically significant correlation was found between working memory capacity, English vocabulary size, and listening proficiency, possibly due to the small sample size and the homogeneous subjects.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.561-564
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• 2005

In this paper, we present a new JPEG (Joint Photograph Experts Group) compression architecture which compresses still image into fixed size of bitstream to use restricted system memory efficiently. The size of bitstream is determined by the complexity of image and the quantization table. But the quantization table is set in advance the complexity of image is the essential factor. Therefore the size of bitstream for high complexity image is large and the size for low complexity image is small. This means that the management of restricted system memory is difficult. The proposed JPEG encoder estimates the size of bitstream using the correlation between consecutive frames and selects the quantization table suited to the complexity of image. This makes efficient use of system memory.

• Journal of Korea Multimedia Society
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• v.14 no.1
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• pp.94-102
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• 2011

To alleviate the size and bandwidth requirement in JPEG2000 system, a new Embedded Compression(EC) algorithm with minor image quality drop is proposed. For both random accessibility and low latency, very simple and efficient hadamard transform based compression algorithm is devised. We reduced LL intermediate memory and code-block memory to about half size and achieved significant memory bandwidth reductions(about 52~73%) through proposed multi-mode algorithms, without requiring any modification in JPEG2000 standard algorithm.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.199-202
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• 2004

NFGM(Nano-Floating Gate Memory) is a very prospective candidate memory for the next generation with MRAM, PRAM, PoRAM. Among these memory devices for the next generation, NFGM has a lot of merits such as a simple low cost fabrication process, improved retention time, lower operating voltages, high speed program/erase time and so on. Therefore, many intensive researches for NFGM have been performed to improve device performance and reliability, which depends on the ability to control particle size, size distribution, crystallity, areal particle density and tunneling oxide quality. In this paper, we investigate the researches for NFGM up to recently.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2012.11a
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• pp.52-53
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• 2012

Belief propagation (BP) is a commonly used global energy minimization algorithm for solving stereo matching problem in 3D reconstruction. However, it requires large memory bandwidth and data size. In this paper, we propose a novel memory-efficient algorithm of BP in stereo matching on the Graphics Processing Units (GPU). The data size and transfer bandwidth are significantly reduced by storing only a part of the whole message. In order to maintain the accuracy of the matching result, the local messages are reconstructed using shared memory available in GPU. Experimental result shows that there is almost an order of reduction in the global memory consumption, and 21 to 46% saving in memory bandwidth when compared to the conventional algorithm. The implementation result on a recent GPU shows that we can obtain 22.8 times speedup in execution time compared to the execution on CPU.

• Journal of the Korean Society of Industry Convergence
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• v.24 no.5
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• pp.531-536
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• 2021

As artificial intelligence technology advances, it is being applied to various application fields. Artificial intelligence is performing well in the field of image recognition and classification. Chip design specialized in this field is also actively being studied. Artificial intelligence-specific chips are designed to provide optimal performance for the applications. At the design task, memory component optimization is becoming an important issue. In this study, the optimal algorithm for the memory size exploration is presented, and the optimal memory size is becoming as a important factor in providing a proper design that meets the requirements of performance, cost, and power consumption.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.6
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• pp.1241-1245
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• 2009

As FFT(Fast Fourier Transform) processor is used in OFDM(Orthogonal Frequency Division Multiplesing) system. According to increase requirement about mobility and broadband, Research about low power and low area FFT processor is needed. So research concern in reduction of memory size and complex multiplier is in progress. Increasing points of FFT increase memory area of FFT processor. Specially, SRU(Signal Reordering Unit) has the most memory in FFT processor. In this paper, we propose a reduced method of memory size of SRU in FFT processor. SRU of 64, 1024 point FFT processor performed implementation by VerilogHDL coding and it verified by simulation. We select the APEX20KE family EP20k1000EPC672-3 device of Altera Corps. SRU implementation is performed by synthesis of Quartus Tool. The bits of data size decide by 24bits that is 12bits from real, imaginary number respectively. It is shown that, the proposed SRU of 64point and 1024point achieve more than 28%, 24% area reduction respectively.

• IEMEK Journal of Embedded Systems and Applications
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• v.6 no.6
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• pp.383-391
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• 2011

As we know the effects of cache memory research, instruction and data caches can be separated for higher performance with Harvard CPUs. In this paper, we shows the efficiency of buffer system in the instruction and data flash storage medium. And we analyzed characteristics of the data and instruction flash and evaluated the performance. Finally, we propose the best buffer structure with an optimal block size and buffer size for the instruction and data flash.

• The Transactions of the Korea Information Processing Society
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• v.7 no.4
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• pp.1082-1091
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• 2000

In Distributed Shared Memory systems, false sharing occurs when two different data items, not shared but accessed by two different processors, are allocated to a single block and is an important factor in degrading system performance. The paper first analyzes shared memory allocation and reference patterns in parallel applications that allocate memory for shared data objects using a dynamic memory allocator. The shared objects are sequentially allocated and generally show different reference patterns. If the objects with the same size are requested successively as many times as the number of processors, each object is referenced by only a particular processor. If the objects with the same size are requested successively much more than the number of processors, two or more successive objects are referenced by only particular processors. On the basis of these analyses, we propose a memory allocation scheme which allocates each object requested by different processors to different pages and evaluate the existing memory allocation techniques for reducing false sharing faults. Our allocation scheme reduces a considerable amount of false sharing faults for some applications with a little additional memory space.