• Journal of Ocean Engineering and Technology
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• v.14 no.3
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• pp.29-34
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• 2000

This paper describes transient responses of a very floating structure subjected to dynamic load induced by waves. A time domain method is applied to the hydroelastic problems for this purpose. The method is based on source-dipole and FEM scheme and on Newmark $\beta$ method to pursuit time step process taking advantage of memory effect. The present procedure is carried out to analyze hydroelastic responses in regular waves and impact responses due to dropping aircraft.

• Proceedings of the Korea Committee for Ocean Resources and Engineering Conference
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• 2000.04a
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• pp.18-22
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• 2000

This paper is transient motions of a very large floating structure subjected to dynamic load induced by wave. A time domain method is applied to the hydroelasticity problems for this purpose. The method is based on source-dipole and FEM scheme and on Newmark $\beta$ method to pursuit time step process taking advantage of the memory effect. The present method is appied to hydroelastic response analysis in regular waves and impact responses due to dropping aircraft.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.80-90
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• 2016

Thanks to superior leakage energy efficiency compared to SRAM cells, STTRAM cells are considered as a promising alternative for a memory element in on-chip caches. However, the main disadvantage of STTRAM cells is high write energy and latency. In this paper, we propose a low-cost write filter (WF) cache which resides between the load/store queue and STTRAM-based L1 data cache. To maximize efficiency of the WF cache, the line allocation and access policies are optimized for reducing energy consumption of STTRAM-based L1 data cache. By efficiently filtering the write operations in the STTRAM-based L1 data cache, our proposed WF cache reduces energy consumption of the STTRAM-based L1 data cache by up to 43.0% compared to the case without the WF cache. In addition, thanks to the fast hit latency of the WF cache, it slightly improves performance by 0.2%.

• IEMEK Journal of Embedded Systems and Applications
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• v.7 no.3
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• pp.151-156
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• 2012

When mounting the sensor device in the way of Plug&Play, sensor device drivers need to be loaded and linked dynamically. Since a sensor node platform is based on small 8 bit MCU, dynamic loading and linking technique used in Windows and Linux can not be applied. In this paper, we present how to link and load dynamically sensor device drivers for sensor device Plug&Play. We implement a prototype and evaluate it to make sure that there is no performance degradation like sensor device driver connection speed and memory usage. Connection speed overhead increases to 0.2ms. Memory usage overhead increases to hundreds byte. It shows that there is no heavy influence in running the actual program.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2001.05a
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• pp.1122-1129
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• 2001

In this work, we propose a new type of HDD suspension featuring shape memory ally (SMA) actuator in order to prevent the contact between the slider and disk. The principal design parameters are obtained from the modal analysis using finite element analysis, and then the dynamic model is established to formulate the control scheme for Non-Contact Start/Stop mode drive. Subsequently, a robust Η$_{\infty}$, control algorithm is designed by integrating experimentally-obtained SMA actuator dynamics to the proposed suspension system. The controller is empirically realized and control results for different load/unload profiles are presented in time domain. In addition, the contact signal between the slider and disk is measured by the electrical resistance method.istance method.

• 제어로봇시스템학회:학술대회논문집
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• 1990.10b
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• pp.1327-1331
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• 1990

A new dual loop controller using color LCD bar graphs with LED back lights has been developed. An optional memory card is used to load or save the controller configuration, which may be a preprogrammed standard package or a user-programmed configuration, in addition to the built-in functions ready for user selection. The bar-graph display is selectable for single-loop or dual-loop use. A high grade of self-tuning functions using a modeling technique is built-in as standard. The controller can accommodate optional plug-in modules for thermocouples, communication, etc. All the options are fully field upgradable.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.1105-1108
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• 1999

In this paper, we propose a new addressing mode, which can be used for programmable image processor to perform image- processing algorithms effectively. Conventional addressing modes are suitable for one-dimensional data processing such as voice, but the proposed addressing mode consider two-dimensional characteristics of image data. The proposed instruction for two-dimensional addressing requires two operands to specify a pixel and doesn't require any change of memory architecture. Combining several instructions to load a pixel-data from an external memory to a register, the proposed instruction reduces code size so that satisfy hish performance and low power requirements of image processor. In addition, it uses inherent two-dimensional characteristics of image data and offers user-friendly instruction to assembler programmer.

• Journal of the Korean Society of Visualization
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• v.14 no.2
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• pp.25-30
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• 2016

The wafer temperature and its uniformity inside the LPCVD chamber were analyzed. The temperature uniformity at the end of the wafer load depends on the heat-insulating cap. The finite difference method was used to investigate the radiation and conduction heat transfer mechanisms, and the temperature field and heat diffusion in the LPCVD chamber was visualized. It was found that the temperature uniformity of the wafers could be controlled by the size and distance of the heat-insulating cap.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.28B no.5
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• pp.327-334
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• 1991

This paper proposes an efficient method of implementing the generalized Hough transform (GHT), which has been hindered by an excessive computing load and a large memory requirement. The conventional algorithm requires a parameter space of 4 dimensions in detection a rotated, scaled, and translated object in an input image. Prior to the application of GHT to the input image, the proposed method determines the angle of rotation and the scaling factor of the test image using the proportion of the edge components between the reference image and test image. With the rotation angle and the scaling factor already determined, the parameter spaceis to be reduced to a simple array of 2 dimensions by applying the unit GHT only one time. The experiments with the image of airplanes reveal that both of the computing time and the requires memory size are reduced by 95 percent, without any degradatationof accuracy, compared with the conventional GHT algorithm.

• Journal of information and communication convergence engineering
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• v.13 no.1
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• pp.27-35
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• 2015

Multiprecision multiplication is the most expensive operation in public key-based cryptography. Therefore, many multiplication methods have been studied intensively for several decades. In Workshop on Cryptographic Hardware and Embedded Systems 2011 (CHES2011), a novel multiplication method called 'operand caching' was proposed. This method reduces the number of required load instructions by caching the operands. However, it does not provide full operand caching when changing the row of partial products. To overcome this problem, a novel method, that is, 'consecutive operand caching' was proposed in Workshop on Information Security Applications 2012 (WISA2012). It divides a multiplication structure into partial products and reconstructs them to share common operands between previous and next partial products. However, there is still room for improvement; therefore, we propose a finely designed operand-caching mode to minimize useless memory accesses when the first row is changed. Finally, we reduce the number of memory access instructions and boost the speed of the overall multiprecision multiplication for public key cryptography.