• Journal of Communications and Networks
• /
• v.17 no.3
• /
• pp.286-295
• /
• 2015

Avionic databuses fulfill a critical function in the connection and communication of aircraft components and functions such as flight-control, navigation, and monitoring. Ethernet-based avionic databuses have become the mainstream for large aircraft owning to their advantages of full-duplex communication with high bandwidth, low latency, low packet-loss, and low cost. As a new generation aviation network communication standard, avionics full-duplex switched ethernet (AFDX) adopted concepts from the telecom standard, asynchronous transfer mode (ATM). In this technology, the switches are the key devices influencing the overall performance. This paper reviews the avionic databus with emphasis on the switch architecture classifications. Based on a comparison, analysis, and discussion of the different switch architectures, we propose a new avionic switch design based on a time-division switch fabric for high flexibility and scalability. This also merges the design concept of space-partition switch fabric to achieve reliability and predictability. The new switch architecture, called space partitioned shared memory switch (SPSMS), isolates the memory space for each output port. This can reduce the competition for resources and avoid conflicts, decrease the packet forwarding latency through the switch, and reduce the packet loss rate. A simulation of the architecture with optimized network engineering tools (OPNET) confirms the efficiency and significant performance improvement over a classic shared memory switch, in terms of overall packet latency, queuing delay, and queue size.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2013.10a
• /
• pp.77-80
• /
• 2013

SURF algorithm is an algorithm to extract feature points and to generate descriptors from input images. It is robust to change of environment such as scale, rotation, illumination and view points. Because of these features, it is used for many image processing applications such as object recognition, constructing panorama pictures and 3D image restoration. But there is disadvantage for real time operation because many recognition algorithms such as SURF algorithm requires a lot of calculations. In this paper, we propose a design of feature extractor and descriptor generator based on SURF for high memory efficiency. The proposed design reduced a memory access and memory usage to operate in real time.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2022.05a
• /
• pp.516-518
• /
• 2022

In this paper, we introduce a dependence of number of nodes of hidden-layer in fall detection system using Long Short-Term Memory that can detect falls. Its training is carried out using the parameter theta(θ), which indicates the angle formed by the x, y, and z-axis data for the direction of gravity using a 3-axis acceleration sensor. In its learning, validation is performed and divided into training data and test data in a ratio of 8:2, and training is performed by changing the number of nodes in the hidden layer to increase efficiency. When the number of nodes is 128, the best accuracy is shown with Accuracy = 99.82%, Specificity = 99.58%, and Sensitivity = 100%.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.12 no.3
• /
• pp.266-269
• /
• 2012

High-efficiency built-in redundancy analysis (BIRA) is presented. The proposed BIRA uses three techniques to achieve a high repair rate using spare mapping registers with adjustable fault tags to reduce area overhead. Simulation results show that the proposed BIRA is a reasonable solution for embedded memories.

• ETRI Journal
• /
• v.31 no.3
• /
• pp.339-341
• /
• 2009

Built-in redundancy analysis (BIRA) is widely used to enhance the yield of embedded memories. In this letter, a new BIRA method for both high repair efficiency and small hardware overhead is presented. The proposed method performs redundancy analysis operations using the spare mapping registers with a covered fault list. Experimental results demonstrate the superiority of the proposed method compared to previous works.

• 제어로봇시스템학회:학술대회논문집
• /
• 1988.10a
• /
• pp.524-527
• /
• 1988

Basic types of bilateral servo systems were described and practical consideration in the bilateral servo controller design was introduced. Power assistance to the operator is essential for high efficiency and accurate force reflection is necessary for dexterous manipulation. This paper shows a controller structure under development at KIMM which employs nonlinear friction compensation and memory based gravity compensation technique for efficiency and dexterity.

• KIPS Transactions on Software and Data Engineering
• /
• v.5 no.12
• /
• pp.623-634
• /
• 2016

Most of existing frequent pattern mining methods address time efficiency and greatly rely on the primary memory. However, in the era of big data, the size of real-world databases to mined is exponentially increasing, and hence the primary memory is not sufficient enough to mine for frequent patterns from large real-world data sets. To solve this problem, there are some researches for frequent pattern mining method based on disk, but the processing time compared to the memory based methods took very time consuming. There are some researches to improve scalability of frequent pattern mining, but their processes are very time consuming compare to the memory based methods. In this paper, we present PPFP as a novel disk-based approach for mining frequent itemset from big data; and hence we reduced the main memory size bottleneck. PPFP algorithm is based on FP-growth method which is one of the most popular and efficient frequent pattern mining approaches. The mining with PPFP consists of two setps. (1) Constructing an IFP-tree: After construct FP-tree, we assign index number for each node in FP-tree with novel index numbering method, and then insert the indexed FP-tree (IFP-tree) into disk as IFP-table. (2) Mining frequent patterns with PPFP: Mine frequent patterns by expending patterns using stack based PUSH-POP method (PPFP method). Through this new approach, by using a very small amount of memory for recursive and time consuming operation in mining process, we improved the scalability and time efficiency of the frequent pattern mining. And the reported test results demonstrate them.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• v.9 no.2
• /
• pp.816-819
• /
• 2005

In Java virtual machine which is the running environment of Java programs, almost every bytecode execution requires data transfers in memory. Data transfer incurs energy consumption and hence minimizing the transfer operation is very important for improving the energy efficiency of JVM. As the number of data transfers for a Java iterative statement is directly proportional to the iteration count, improving the energy efficiency of iterative statement is crucial to keep the energy efficiency of JVM high. This paper analyzes Java iterative statement at bytecode level and proposes some points how to improve the energy efficiency.

• Journal of the Korea Society of Computer and Information
• /
• v.17 no.7
• /
• pp.1-11
• /
• 2012

As process technology scales down, the number of cores integrated into a processor increases dramatically, leading to significant performance improvement. Especially, the GPU(Graphics Processing Unit) containing many cores can provide high computational performance by maximizing the parallelism. In the GPU architecture, the access latency to the main memory becomes one of the major reasons restricting the performance improvement. In this work, we analyze the performance improvement of the 3D GPU architecture compared to the 2D GPU architecture quantitatively and investigate the potential problems of the 3D GPU architecture. In general, memory instructions account for 30% of total instructions, and global/local memory instructions constitutes 60% of total memory instructions. Therefore, the performance of the 3D GPU is expected to be improved significantly compared to the 2D GPU by reducing the delay of memory instructions. However, according to our experimental results, the 3D architecture improves the GPU performance only by 2% compared to the 2D architecture due to the memory bottleneck, since the performance reduction due to memory bottleneck in the 3D GPU architecture increases by 245% compared to the 2D architecture. This paper provides the guideline for suitable memory design by analyzing the efficiency of the memory architecture in 3D GPU architecture.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.27 no.4
• /
• pp.775-783
• /
• 2017

As interest in cloud computing grows, the number of users using cloud computing services is increasing. However, cloud computing technology has been steadily challenged by security concerns. Therefore, various security breaches are springing up to enhance the system security for cloud services users. In particular, research on detection of malicious VM (Virtual Machine) is actively underway through the introspecting virtual machines on the cloud platform. However, memory analysis technology is not used as a monitoring tool in the environments where multiple virtual machines are run on a single server platform due to obstructive monitoring overhead. As a remedy to the challenging issue, we proposes a computationally efficient instance memory introspection scheme to minimize the overhead that occurs in memory dump and monitor it through a partial memory monitoring based on the well-defined kernel memory map library.