• Journal of the Institute of Convergence Signal Processing
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• 제8권1호
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• pp.58-62
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• 2007

Digital communication is important for reliability and mobilization of the multi-channel communication systems. Transmitting and receiving data for the mobilization should be possible in anywhere and in anytime. And this system must be designed light weight small size and low power. One are essential technology for implementing the mobile wireless communication system on the age of ubiquotos. Requirements in constructing such communication field are followings. At first data transmitting and receiving should be carried out by a simple command. Second, the device should be designed as hand-hold type and low power consumption. Third, data communication should be reliable. As one of examples, car to car system which is popular in the market is introduced here, All traffic information in highway is transmitted from one car to another by using this system which can prevent possible traffic accident. This paper shows the design of a digital data communication system with CC1020 chip. This CC1020 makes easy frequency selection and easy switch from the transmit mode to the receive mode by simple setting of a memory register in the chip. The transmit power of this system is designed 10dBm and its communication range is about 100m. The power supplied this system is 3V considered as low power. The sleep mode can be easily entered during transmit mode or receive mode. We shows the program algorithm of CC1020 and interface circuit between MCU and CC1020. We shows the Photo of the CC1020 Module and Atmega128 Module.. We analysed the receiver rate with this system.

• Journal of the Korean Ceramic Society
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• 제39권12호
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• pp.1128-1132
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• 2002

$ReMnO_3$(Re:Y, Ho, Er) thin films were prepared by MOCVD method available to non-volatile memory device with MFS-FET structure. $ReMnO_3$ thin films were deposited on the Si(100) substrate at 700${\circ}C$ for 2h. When the films were post-annealed at 900${\circ}C$ for 1h in air, the single phase of hexagonal $ReMnO_3$ thin films were detected. Ferroelectric properties of $ReMnO_3$ thin films were dependent on the degree of c-axis orientation in the single phase of hexagonal structure and remnant polarization (Pr) of $YMnO_3$ thin films with high degree of c-axis orientation was 105 nC/$cm^2$. Leakage current density was dependent on the grain size of microstructure and that of $YMnO_3$ thin films with grain size of 100∼150 nm was $10^{-8}$ A/$cm^2$ at applied voltage of 0.5 V.

• Journal of the Korean Magnetics Society
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• 제10권5호
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• pp.210-219
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• 2000

The magnetoresistance characteristics of FeN/Co/Cu/Co and FeN/Co/Cu/Co/Cu/Co/FeN multilayers using ferromagnetic iron-nitrides (FeN) has been studied. The microstructure of FeN film is the mixed ${\alpha}$-Fe and $\varepsilon$-Fe$_3$N phase on the condition that the flow rate of N$_2$ gas is over 0.4 sccm. The magnetoresistance effect is observed because of shape magnetic anisotropy induced by needle-shaped $\varepsilon$-Fe$_3$N phase. This magnetoresistance effect changes, because the degree that the shape magnetic anisotropy adheres to the adjacent Co pinned layer is varied according to the flow rate of N$_2$ gas and the thickness of FeN film. The best magnetoresistance effect is obtained on the condition that the thickness of Co free layer is 70 ${\AA}$ and the maximum MR ratio(%) value of 3.2% shows in the FeN(250 ${\AA}$)/Co(70 ${\AA}$)/Cu(25 ${\AA}$)/Co(70 ${\AA}$)/Cu(25 ${\AA}$)/Co(70 ${\AA}$)/FeN(250 ${\AA}$) mutilayer film which is fabricated at the N, gas flow rate of 0.5 sccm and the FeN film thickness of 250 ${\AA}$. Four steps are observed in the magnetoresistance curve owing to this difference of coercive force, because respective magnetic layers in the multilayer possess different coercive forces. These effects observed in these mutilayer films can be expected to application to the memory device the same MRAM as can carry out simultaneously four signals.

• Journal of the Microelectronics and Packaging Society
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• 제8권3호
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• pp.49-53
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• 2001

Vortical etching experiments of ($SrBi_2Ta_2O_9$)/Si thin films have been performed by using the inductively coupled plasma reactive ion etching (ICP-ME) apparatus. The purposes of these experiments are to get the effective area of vertical surface. Because this technology is very important to get good qualities of ferroelectric gate structure, capacitor and the minimum parasitic effects related to the excellent performances of the FRAM (Ferroelectric Random Access Memory) device. The reacting gases were Ar and $Cl_2$gases, and various $Ar/C1_2$flow ratios were used. The etching experiments were carried out at various RF powers such as 700, 700, 500W and at various DC powers such as 200, 150, 100, 50W, respectively. The maximum etch rate of $SrBi_2Ta_2O_9$/Si thin films was 1050 A/min at the $Ar/C1_2$ gas ratio of 20/16, RF power of 700 W and DC power of 200 W. From the SEM (scanning electron microscopy) image of the SBT thin films, the wall angle was as good as about $82^{\circ}$.

• Journal of the Institute of Electronics Engineers of Korea SP
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• 제42권5호
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• pp.85-94
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• 2005

Display characterization, deriving the relationship between digital input values and the corresponding CIEXYZ tri-stimulus values, is important to reproduce the accurate color in color management system. The relationship can be estimated from the nine channel TRCs(tone response curves) and the result of this characterization method is better than that of using three channel TRCs. However, the inverse display characterization using nine channel TRCs cannot be directly inverted because the CIEXYZ values corresponding to each of RGB values are inseparable. Accordingly, inverse display characterization is usually implemented by the 3D-LUT (look-up table) method. Although the result of 3B-LUT is accurate, creating the 3D-LUT requires a lot of memory space and considerable amount of measurements. Therefore the inverse characterization method is proposed based on the modeling of channel-dependent values and nine channel inverse process based on the GOG(gain, offset gamma) model. The proposed method enhances the accuracy of display characterization and reduces the complexity and the number of measurements data required for accuracy in 3-D LUT.

• Journal of the Korea Institute of Information and Communication Engineering
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• 제22권1호
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• pp.100-108
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• 2018

This paper describes a design of scalable RSA public-key cryptography processor supporting four key lengths of 512/1,024/2,048/3,072 bits. The modular multiplier that is a core arithmetic block for RSA crypto-system was designed with 32-bit datapath, which is based on the CIOS (Coarsely Integrated Operand Scanning) Montgomery modular multiplication algorithm. The modular exponentiation was implemented by using L-R binary exponentiation algorithm. The scalable RSA crypto-processor was verified by FPGA implementation using Virtex-5 device, and it takes 456,051/3,496347/26,011,947/88,112,770 clock cycles for RSA computation for the key lengths of 512/1,024/2,048/3,072 bits. The RSA crypto-processor synthesized with a $0.18{\mu}m$ CMOS cell library occupies 10,672 gate equivalent (GE) and a memory bank of $6{\times}3,072$ bits. The estimated maximum clock frequency is 147 MHz, and the RSA decryption takes 3.1/23.8/177/599.4 msec for key lengths of 512/1,024/2,048/3,072 bits.

• Journal of the Institute of Electronics Engineers of Korea TC
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• 제41권9호
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• pp.73-80
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• 2004

In this paper, we present the cell resequencing buffer to solve the cell sequence integrity problem of the Cyclic banyan network that is a high-performance fault-tolerant cell switch. By offering multiple paths between input ports and output ports, using the deflection self-routing, the Cyclic banyan switch offer high reliability, and it also solves congestion problem for the internal links of the switch. By the way, these multiple paths can be different lengths for each other. Therefore, the cells departing from an identical source port and arriving at an identical destination port can reach to the output port as the order that is different from the order arriving at input port. The proposed cell resequencing buffer is a hardware sliding window mechanism. to solve such cell sequence integrity problem. To calculate the size of sliding window that cause the prime cost of the presented device, we analyzed the distribution of the cell delay through the simulation analyses under traffic load that have a nonuniform address distribution that express tile Property of traffic of the Internet. Through these analyses, we found out that we can make a cell resequencing buffer by which the cell sequence integrity is to be secured, by using a, few of ordinary memory and control logic. The cell resequencing buffer presented in this paper can be used for other multiple paths switching networks.

• Journal of the Microelectronics and Packaging Society
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• 제9권4호
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• pp.11-16
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• 2002

In this study, the dry etching characteristics of $SrBi_2Ta_2O_9$ (SBT) thin films were investigated by using ICP-RIE (inductively coupled plasma-reactive ion etching). The etching damage and degradation were analyzed with XPS (X-ray photoelectron spectroscopy) and C-V (Capacitance-Voltage) measurement. The etching rate increased with increasing the ICP power and the capacitively coupled plasma (CCP) power. The etch rate of 900$\AA$/min was obtained with 700 W of ICP power and 200 W of CCP power. The main problem of dry etching is the degradation of the ferroelectric material. The damage-free etching characteristics were obtained with the $Ar/C1_2/CHF_3$ gas mixture of 20/14/2 when the ICP power and CCP power were biased at 700 W and 200 W, respectively. The experimental results show that the dry etching process with ICP-RIE is applicable to the fabrication of the single transistor type ferroelectric memory device.

• Journal of the Korea Institute of Information and Communication Engineering
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• 제18권3호
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• pp.541-550
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• 2014

This paper describes a multi-scale user interaction based tiled display visualization system using multiple input devices for monitoring and analyzing Geostationary Ocean Color Imager (GOCI) observation satellite imagery. This system provides multi-touch screen, Kinect motion sensing, and moblie interface for multiple users to control the satellite imagery either in front of the tiled display screen or far away from a distance to view marine environmental or climate changes around Korean peninsular more effectively. Due to a large amount of memory required for loading high-resolution GOCI satellite images, we employed the multi-level image load technique where the image was divided into small tiled images in order to reduce the load on the system and to be operated smoothly by user manipulation. This system performs the abstraction of common input information from multi-user Kinect motion and gestures, multi-touch points and mobile interaction information to enable a variety of user interactions for any tiled display application. In addition, the unit of time corresponding to the selected date of the satellite images are sequentially displayed on the screen and multiple users can zoom-in/out, move the imagery and select buttons to trigger functions.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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• pp.257-257
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• 2007

고밀도 FeRAM (Ferroe!ectric Random Access Memory) 소자를 개발하기 위해서는 강유전체 물질을 이용한 안정적인 스텍형의 커패시터 개발이 필수적이다. 특히 $(Bi,La)_4Ti_3O_{12}$ (BLT) 강유전체 물질을 이용하는 경우에는 낮은 열처리 온도에서도 균질하고 높은 값의 잔류 분극 값을 확보하는 것이 가장 중요한 과제 중의 하나이다. 불행히도, BLT 물질은 a-축으로는 약 $50\;{\mu}C/cm^2$ 정도의 높은 잔류 분극 값을 갖지만, c-축 방향으로는 $4\;{\mu}C/cm^2$ 정도의 낮은 잔류 분극 값을 나타내는 동의 강한 비등방성 특성을 보인다. 따라서 BLT 박막에서 각각 입자들의 크기 및 결정 방향성을 세밀하게 제어하는 것은 무엇보다 중요하다. 본 연구에서는 16 Mb의 1T/1C (1-transistor/1-capacitor) 형의 FeRAM 소자를 BLT 박막을 적용하여 제작하였다. 솔-젤 (sol-gel) 용액을 이용하여 스핀코팅법으로 BLT 박막을 증착하고, 후속 열처리 공정을 RTP (rapid thermal process) 공정을 이용하여 수행하였다. 커패시터의 하부 전극 및 상부 전극은 각각 Pt/IrOx/lr 및 Pt을 적용하였다. 반응성 이온 에칭 (RIE: reactive ion etching) 공정을 이용하여 커패시터를 형성시킨 후, 32k-array (unit capacitor: $0.68\;{\mu}m$) 패턴에서 측정한 스위칭 분극 (dP=P*-P^) 값은 약 $16\;{\mu}C/cm^2$ 정도이고, 웨이퍼 내에서의 균일도도 2.8% 정도로 매우 우수한 특성을 보였다. 그러나 단위 셀들의 특성을 평가하기 위하여 bit-line의 전압을 측정한 결과, 약 10% 정도의 커패시터에서 불량이 발생하였다. 그리고 이러한 불량 젤들은 매우 불규칙적으로 분포함을 확인할 수 있었다. 이러한 불량 원인을 파악하기 위하여 양호한 젤과 불량이 발생한 셀에서의 BLT 박막의 미세구조를 분석하였다. 양호한 셀의 BLT 박막 입자들은 불량한 셀에 비하여 작고 비교적 균일한 크기를 갖고 있었다. 이에 비하여 불량한 셀에서의 BLT 박막에는 과대 성장한 입자들이 존재하고 이에 따라서 입자 크기가 매우 불균질한 것으로 확인되었다. 또 이러한 과대 성장한 입자들은 거의 모두 c-축 배향성을 나타내었다. 이상의 실험 결과들로부터, BLT 박막을 이용하여 제작한 FeRAM 소자에서 발생하는 불규칙한 셀 불량의 주된 원인은 c-축 배향성을 갖는 과대 성장한 입자의 생성임을 알 수 있었다. 즉 BLT 박막을 이용하여 FeRAM 소자를 제작하는 경우, 균일한 크기의 입자 및 c-축 배향성의 입자 억제가 매우 중요한 기술적 요소임을 알 수 있었다.