• The KIPS Transactions:PartB
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• v.12B no.2 s.98
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• pp.181-190
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• 2005

Developing wireless internet service and mobile devices, mechanisms for web service across are various. However, the existing web infrastructure and content were designed for desktop computers and arc not well-suited for other types of accesses, e.g. PDA or mobile Phone that have less processing power and memory, small screens, limited input facilities, or network bandwidth etc. Thus, there is a growing need for transcoding techniques that provide that ability to browse the web through mobile devices. However, previous researches on existing web contents transcoding are service provider centric, which does not accurately reflect the user's continuously changing interest. In this paper, we presents a transcoding technique involved in making existing news contents based on XML available via customized wireless service, mobile phone.

• Journal of the Korean Society of Safety
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• v.29 no.1
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• pp.47-53
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• 2014

The application of advanced Main Control Room(MCR) is accompanied with lots of changes and different forms and features through the virtue of new digital technologies. The characteristics of these digital technologies and devices give many opportunities to the interface management, and can be integrated into a compact single workstation in advanced MCR so that workers can operate the plant with minimum physical burden under any operation conditions. However, these devices may introduce new types of human errors and thus a means to evaluate and prevent such errors is needed, especially those related to characteristics of digital devices. This paper reviewed the new type of human error hazards of tasks based on digital devices and surveyed researches on physiological assessment related to human error. An experiment was performed to verify human error hazards by physiological responses such as EEG which was measured to evaluate the cognitive workload of operators. And also, the performances of four tasks which are representative in human error hazard tasks based on digital devices were compared. Response time, ${\beta}$ power spectrum rate of each task by EEG, and mental workload by NASA-TLX were evaluated. In the results of the experiment, the rate of the ${\beta}$ power was increased in the task 1 and task 4 which are searching and navigating task and memory task of hierarchical information, respectively. In case of the mental workload, in most of evaluation items, task 1 and 4 were highly rated comparatively. In this paper, human error hazards might be identified by highly cognitive workload. Conclusively, it was concluded that the predictive method which is utilized in this paper and an experimental verification can be used to ensure the safety when applying the digital devices in Nuclear Power Plants (NPPs).

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.581-584
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• 2006

Cellular phones have been popularized and some of them even have access to the Internet. But the utilization of mobile phones has not been for education but only focused on particular services due to the text-based low capacity. This thesis proposes a multimedia education system using cell phones with SMIL. We can decrease the size of the parser and refute the resources of CPU by designing SMIL tag only, which is needed for multimedia education. In addition, the macro method for producing information for lectures will make possible decreased transmission quantity of multimedia contents and increased transmission efficiency. This will lead to overcoming the matter of insufficient CPU and memory, which is common to most mobile phone terminals.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.313-315
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• 2010

In this paper, we describe research results of developing hardware rasterizer that is applicable to mobile 3D graphics system, designed in SIMD architecture and verified in FPGA. Tile-based scan conversion unit is designed like SIMD architecture running four tiles simultaneously and each tile traverses pixels hierarchical in 3-level so that visiting counts is minimized. As experimental results, $8{\times}8$ is the most efficient size of tile and the last step of tile traversing is performed on $2{\times}2$ sized subtile. The rasterizer supports flat shading and gouraud shading and texture mapper supports affine mapping and perspective corrected mapping. Also, texture mapper supports point sampling mode and bilinear interpolating sampling mode and two types of wrapping modes and various blending modes. The rasterzer operates as 120Mhz on xilinx vertex4 $l{\times}100$ device. To easy verification, texture memory and frame buffer are generated as block rom and block ram.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.8
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• pp.1471-1479
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• 2017

This paper describes a design of RSA public-key cryptography processor supporting key length of 2,048 bits. A modular multiplier that is core arithmetic function in RSA cryptography was designed using word-based Montgomery multiplication algorithm, and a modular exponentiation was implemented by using Left-to-Right (LR) binary exponentiation algorithm. A computation of a modular multiplication takes 8,386 clock cycles, and RSA encryption and decryption requires 185,724 and 25,561,076 clock cycles, respectively. The RSA processor was verified by FPGA implementation using Virtex5 device. The RSA cryptographic processor synthesized with 100 MHz clock frequency using a 0.18 um CMOS cell library occupies 12,540 gate equivalents (GEs) and 12 kbits memory. It was estimated that the RSA processor can operate up to 165 MHz, and the estimated time for RSA encryption and decryption operations are 1.12 ms and 154.91 ms, respectively.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.502-502
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• 2007

Current thin film process using memory device fabrication process use expensive processes such as manufacturing of photo mask, coating of photo resist, exposure, development, and etching. However, direct printing technology has the merits about simple and cost effective processes because inks are directly injective without mask. And also, this technology has the advantage about fabrication of fine pattern line on various substrates such as PCB, FCPB, glass, polymer and so on. In this work, we have fabricated the fine and thick metal pattern line for the electronic circuit board using metal ink contains Ag nano-particles. Metal lines are fabricated by two types of printing methods. One is a conventional printing method which is able to quick fabrication of fine pattern line, but has various difficulties about thick and high resolution DPI(Dot per Inch) pattern lines because of bulge and piling up phenomenon. Another(Second) methods is sequential printing method which has a various merits of fabrication for fine, thick and high resolution pattern lines without bulge. In this work, conductivities of metal pattern line are investigated with respect to printing methods and pattern thickness. As a result, conductivity of thick pattern is about several un.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.169-170
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• 2006

In this study, ultra thin films of ferroelectric vinylidene fluoride-trifluoroethylene (VF2-TrFE) copolymer were fabricated on degenerated Si (n+, $0.002\;{\Omega}{\cdot}cm$) using by spin coating method. A 1~5 wt% diluted solution of purified vinylidene fluoride-trifluoroethylene (VF2:TrFE=70:30) in a dimethylformamide (DMF) solvent were prepared and deposited on silicon wafers at a spin rate of 2000~5000rpm for 30 seconds. After annealing in a vacuum ambient at $200^{\circ}C$ for 60 min, upper gold electrodes were deposited by vacuum evaporation for electrical measurement. X-ray diffraction results showed that the VF2-TrFE films on Si substrates had $\beta$-phase of copolymer structures. The capacitance on $n^+$-Si(100) wafer showed hysteresis behavior like a butterfly shape and this result indicates clearly that the dielectric films have ferroelectric properties. The typical measured remnant polarization (2Pr) and coercive filed (EC) values measured using a computer controlled a RT-66A standardized ferroelectric test system (Radiant Technologies) were about $0.54\;C/cm^2$ and 172 kV/cm, respectively, in an applied electric field of ${\pm}0.75\;MV/cm$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.631-634
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• 2009

Recent advances in wireless communication, electronics, MEMS device, sensor and battery technology have made it possible to manufacture low-cost, low-power, multi-function tiny sensor nodes. A large number of tiny sensor nodes form sensor network through wireless communication. Sensor networks represent a significant improvement over traditional sensors, research on Zigbee wireless image transmission has been a topic in industrial and scientific fields. In this paper, we design a Zigbee wireless image sensor node and multimedia monitoring server system. It consists of embedded processor, memory, CMOS image sensor, image acquisition and processing unit, Zigbee RF module, power supply unit and remote monitoring server system. In the future, we will further improve our Zigbee wireless image sensor node and monitoring server system. Besides, energy-efficient Zigbee wireless image transmission protocol and interworking with mobile network will be our work focus.

• Nuclear Engineering and Technology
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• v.53 no.10
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• pp.3406-3412
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• 2021

A real-time digital time-stamp sorting algorithm used in the In-Beam positron emission tomography (In-Beam PET) is presented. The algorithm is operated in the field programmable gate array (FPGA) and a small amount of registers, MUX and memory cells are used. It is developed for sorting the data of annihilation event from front-end circuits, so as to identify the coincidence events efficiently in a large amount of data. In the In-Beam PET, each annihilation event is detected by the detector array and digitized by the analog to digital converter (ADC) in Data Acquisition Unit (DAQU), with a resolution of 14 bits and sampling rate of 50 MS/s. Test and preliminary operation have been implemented, it can perform a sorting operation under the event count rate up to 1 MHz per channel, and support four channels in total, count rate up to 4 MHz. The performance of this algorithm has been verified by pulse generator and ²²Na radiation source, which can sort the events with chaotic order into chronological order completely. The application of this algorithm provides not only an efficient solution for selection of coincidence events, but also a design of electronic circuit with a small-scale structure.

• Journal of IKEEE
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• v.25 no.3
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• pp.473-478
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• 2021

Although CNTFETs have attracted great attention due to their ability to increase semiconductor device performance by about 13 times, the commercialization of CNTFETs has been challenging because of the immature deposition process of CNTs. To overcome these difficulties, circuit design method considering the known limitations of the CNTFET manufacturing process is receiving increasing attention. SRAM is a major element constituting microprocessor and is regularly and repeatedly positioned in the cache memory; so, it has the advantage that CNTs can be more easily and densely deposited in SRAM than other circuit blocks. In order to take these advantages, this paper presents a circuit design method for SRAM cells considering CNT density and then evaluates its performance improvement using HSPICE simulation. As a result of simulation, it is found that when CNTFET is applied to SRAM, the gate width can be reduced by about 1.7 times and the read speed also can be improved by about 2 times when the CNT density was increased in the same gate width.