• Title/Summary/Keyword: memory controller

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Design of FPGA-based Wearable System for Checking Patients (환자 체크를 위한 FPGA 기반 웨어러블 시스템 설계)

  • Kang, Sungwoo;Ryoo, Kwangki
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2017.10a
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    • pp.477-479
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    • 2017
  • With the recent advances in medical technology and health care, the prevention and treatment of diseases has developed. Accordingly aging has rapidly progressed. In this life span and aging society, demand for diagnostic centered medical care is increasing rapidly. In this paper, we propose a wearable patient check system based on FPGA that can be controlled by sensors. In the existing hospital, a doctor or nurse visited the patient every hour to check the condition. However, in this paper, patients, doctors and nurses can check the patient's condition at the desired time using patient check system. In addition, the tilt sensor is used for the patient who is uncomfortable to easily control. The proposed FPGA-based hardware architecture consists of an algorithm for enlarged image processing, a TFT-LCD Controller, a CIS Controller, and a Memory Controller to output the patient's status image. Implemented and validated using the DE2-115 test board with Cyclone IV EP4CE115F29C7 FPGA device and its operating frequency is 50MHz.

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Design and Fabrication of Low Power Sensor Network Platform for Ubiquitous Health Care

  • Lee, Young-Dong;Jeong, Do-Un;Chung, Wan-Young
    • 제어로봇시스템학회:학술대회논문집
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    • 2005.06a
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    • pp.1826-1829
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    • 2005
  • Recent advancement in wireless communications and electronics has enabled the development of low power sensor network. Wireless sensor network are often used in remote monitoring control applications, health care, security and environmental monitoring. Wireless sensor networks are an emerging technology consisting of small, low-power, and low-cost devices that integrate limited computation, sensing, and radio communication capabilities. Sensor network platform for health care has been designed, fabricated and tested. This system consists of an embedded micro-controller, Radio Frequency (RF) transceiver, power management, I/O expansion, and serial communication (RS-232). The hardware platform uses Atmel ATmega128L 8-bit ultra low power RISC processor with 128KB flash memory as the program memory and 4KB SRAM as the data memory. The radio transceiver (Chipcon CC1000) operates in the ISM band at 433MHz or 916MHz with a maximum data rate of 76.8kbps. Also, the indoor radio range is approximately 20-30m. When many sensors have to communicate with the controller, standard communication interfaces such as Serial Peripheral Interface (SPI) or Integrated Circuit ($I^{2}C$) allow sharing a single communication bus. With its low power, the smallest and low cost design, the wireless sensor network system and wireless sensing electronics to collect health-related information of human vitality and main physiological parameters (ECG, Temperature, Perspiration, Blood Pressure and some more vitality parameters, etc.)

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Active Shape Control of Composite Beam Using Shape Memory Alloy Actuators (형상기억합금 작동기를 이용한 복합재 보의 능동 형상 제어)

  • Yang, Seung-Man;Roh, Jin-Ho;Han, Jae-Hung;Lee, In
    • Composites Research
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    • v.17 no.4
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    • pp.18-24
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    • 2004
  • In this paper, active shape control of composite structures actuated by shape memory alloy (SMA) wires is presented. The thermo-mechanical behaviors of SMA wires were experimentally measured. Hybrid composite structures were established by attaching SMA actuators on the surfaces of graphite/epoxy composite beams using bolt-joint connectors. SMA actuators were activated by phase transformation, which induced by temperature rising over austenite finish temperature. In this paper, electrical resistive heating was applied to the hybrid composite structures to activate the SMA actuators. For (aster and more accurate shape/deflection control of the hybrid composite structure, PID feedback controller was designed from numerical simulations and experimentally applied to the SMA actuators.

Modeling and control of a flexible continuum module actuated by embedded shape memory alloys

  • Hadi, Alireza;Akbari, Hossein
    • Smart Structures and Systems
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    • v.18 no.4
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    • pp.663-682
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    • 2016
  • Continuum manipulators as a kind of mechanical arms are useful tools in special robotic applications. In medical applications, like colonoscopy, a maneuverable thin and flexible manipulator is required. This research is focused on developing a basic module for such an application using shape memory alloys (SMA). In the structure of the module three wires of SMA are uniformly distributed and attached to the circumference of a flexible tube. By activating wires, individually or together, different rotation regimes are provided. SMA model is used based on Brinson work. The SMA model is combined to model of flexible tube to provide a composite model of the module. Simulating the model in Matlab provided a platform to be used to develop controller. Complex and nonlinear behavior of SMA make the control problem hard especially when a few SMA actuators are active simultaneously. In this paper, position control of the two degree of freedom module is under focus. An experimental control strategy is developed to regulate a desired position in the module. The simulation results present a reasonable performance of the controller. Moreover, the results are verified through experiments and show that the continuum module of this paper would be used in real modular manipulators.

System Level Architecture Evaluation and Optimization: an Industrial Case Study with AMBA3 AXI

  • Lee, Jong-Eun;Kwon, Woo-Cheol;Kim, Tae-Hun;Chung, Eui-Young;Choi, Kyu-Myung;Kong, Jeong-Taek;Eo, Soo-Kwan;Gwilt, David
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.5 no.4
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    • pp.229-236
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    • 2005
  • This paper presents a system level architecture evaluation technique that leverages transaction level modeling but also significantly extends it to the realm of system level performance evaluation. A major issue lies with the modeling effort. To reduce the modeling effort the proposed technique develops the concept of worst case scenarios. Since the memory controller is often found to be an important component that critically affects the system performance and thus needs optimization, the paper further addresses how to evaluate and optimize the memory controllers, focusing on the test environment and the methodology. The paper also presents an industrial case study using a real state-of-the-art design. In the case study, it is reported that the proposed technique has helped successfully find the performance bottleneck and provide appropriate feedback on time.

A Structure Distributed Processing Method in Data Flow Systems (Data Flow 시스템에서 구조체 분산 처리 방식)

  • Maeng, S.Y.;Hyun, W.M.;Ha, Y.H.;Lim, I.C.
    • Proceedings of the KIEE Conference
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    • 1987.07b
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    • pp.1125-1128
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    • 1987
  • This paper proposes a method which distributes the structure data represented by a tree and handles it. To distribute and handle the structure data, this method partitions a structure data and distributes the partitioned structure in multiple processing element and allocates the partitioned structure. Each processing element includes the structure memory to store the partitioned structure and the structure controller to handle efficiently the distributed structure. As the structure is distributed and is stored in the structure memory and is handled by the structure controller, the processing time is reduced.

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Implementation of AHB1-AHB2 Multi-Bus Architecture Using Memory Selector (메모리 셀렉터를 이용한 AHB1-AHB2 다중버스 아키텍처 구조 구현)

  • Lee, Keun-Hwan;Lee, Kook-Pyo;Yoon, Yung-Sup
    • Proceedings of the IEEK Conference
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    • 2008.06a
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    • pp.527-528
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    • 2008
  • In this paper, several cases of multi-shared bus architecture are discussed and in order to decrease the bridge latency, the architecture introducing a memory decoder is proposed. Finally, a LCD controller using DMA master is integrated in this bus architecture that is verified due to RTL simulation and FPGA board test. DMA, LCD line buffer and SDRAM controller are normally operated in the timing simulation using ModelSim tool, and the LCD image is confirmed in the real FPGA board containing LCD panel.

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Design of the User Interface for T33521 (T33521에 대한 사용자 인터페이스 설계)

  • 김현경;곽윤식
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2002.11a
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    • pp.409-412
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    • 2002
  • In this paper, We present a designe method for the PC User Interface. Also, the system implementation for T33521 is a interface controller of MMC and SSFCD card which operated with limit speed 12Mbit/s in USB Ver.1.1 and under circumstances windows 95, 98 and Mac Os 8.1. Using this controller, we implemented functional design such as automatic reading, memory block read/write, and file property of 8M/16M flash memory and 32M SMC.

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The Development of Programmable Controller Using Binary-Decision Method (Binary-Decision 방식을 이용한 프로그래머블 콘트롤러의 개발에 관한 연구)

  • 전병실;이준환;엄경배
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.12 no.5
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    • pp.492-504
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    • 1987
  • The Binary Decision method can evaluate any switching function in the number of steps not exceeding the number of input variables. A Binary Decision Programmable Controller module is designed using this method so as to improve scan speed. A compiler system is also developed to relieve the memory problem which the Binary Decision method entails. A communication channel between MDS and BD-PC modules is also constructed to load the compiled BD-PC object program into the memory of BD machine.

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Asynchronous State Feedback Control for SEU Mitigation of TMR Memory (비동기 상태 피드백 제어를 이용한 TMR 메모리 SEU 극복)

  • Yang, Jung-Min;Kwak, Seong-Woo
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.57 no.8
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    • pp.1440-1446
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    • 2008
  • In this paper, a novel TMR (Triple Modular Redundancy) memory structure is proposed using state feedback control of asynchronous sequential machines. The main ability of the proposed structure is to correct the fault of SEU (Single Event Upset) asynchronously without resorting to the global synchronous clock. A state-feedback controller is combined with the TMR realized as a closed-loop asynchronous machine and corrective behavior is operated whenever an unauthorized state transition is observed so as to recover the failed state of the asynchronous machine to the original one. As a case study, an asynchronous machine modelling of TMR and the detailed procedure of controller construction are presented. A simulation results using VHDL shows the validity of the proposed scheme.