• Proceedings of the KSME Conference
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• 2004.04a
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• pp.706-709
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• 2004

A numerical method was developed that imposes constraint condition on the order parameters in martensitic phase transformation. In the method, an amplitude function having values of 1 or 0 was multiplied to transformation rates. The merit of the method is that the imposition of the constraint condition is more straightforward than a method with Lagrangian multiplier and easy to implement in the tangent modulus method. The developed method is applied to three-dimensional finite element analyses of single and poly crystalline shape memory alloys.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.1098-1100
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• 2005

The floorplanning problem is an essential design step in VLSI layout design and it is how to place rectangular modules as density as possible. And then, as the DSM advances, the VLSI chip becomes more congested even though more metal layers are used for routing. Usually, a VLSI chip includes several buses. As design increases in complexity, bus routing becomes a heavy task. To ease bus routing and avoid unnecessary iterations in physical design, we need to consider bus planning in early floorplanning stage. In this paper, we propose a floorplanning method for topological constraint consisting of bus constraint and memory constraint. The proposed algorithms based on Genetic Algorithm(GA) is adopted a sequence pair. For selection control, new objective functions are introduced for topological constraint. Studies on floor planning and cell placement have been reported as being applications of GA to the LSI layout problem. However, no studies have ever seen the effect of applying GA in consideration of topological constraint. Experimental results show improvement of bus and memory constraint.

• ETRI Journal
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• v.26 no.1
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• pp.21-26
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• 2004

This paper proposes a new architecture for a Viterbi decoder with an efficient memory management scheme. The trace-back operation is eliminated in the architecture and the memory storing intermediate decision information can be removed. The elimination of the trace-back operation also reduces the number of operation cycles needed to determine decision bits. The memory size of the proposed scheme is reduced to 1/($5{\times}$ constraint length) of that of the register exchange scheme, and the throughput is increased up to twice that of the trace-back scheme. A Viterbi decoder complying with the IS-95 reverse link specification is designed to verify the proposed architecture. The decoder has a code rate of 1/3, a constraint length of 9, and a trace-forward depth of 45.

• Journal of Korean Institute of Industrial Engineers
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• v.27 no.4
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• pp.406-412
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• 2001

IP address lookup is to determine the next hop destination of an incoming packet in the router. The address lookup is a major bottleneck in high performance router due to the increased routing table sizes, increased traffic, higher speed links, and the migration to 128 bits IPv6 addresses. IP lookup time is dependent on data structure of lookup table and search scheme. In this paper, we propose a new approach to build a lookup table that satisfies the memory constraint. The design of lookup table is formulated as an optimization problem. The objective is to minimize average depth from the root node for lookup. We assume that the frequencies with which prefixes are accessed are known and the data structure is level compressed trie with branching factor $\kappa$ at the root and binary at all other nodes. Thus, the problem is to determine the branching factor k at the root node such that the average depth is minimized. A heuristic procedure is proposed to solve the problem. Experimental results show that the lookup table based on the proposed heuristic has better average and the worst-case depth for lookup.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.7
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• pp.2914-2935
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• 2016

With the increasing popularization of cloud computing, how to reduce physical energy consumption and increase resource utilization while maintaining system performance has become a research hotspot of virtual machine deployment in cloud platform. Although some related researches have been reported to solve this problem, most of them used the traditional heuristic algorithm based on greedy algorithm and only considered effect of single-dimensional resource (CPU or Memory) on energy consumption. With considerations to multi-dimensional resource utilization, this paper analyzed impact of multi-dimensional resources on energy consumption of cloud computation. A multi-dimensional resource constraint that could maintain normal system operation was proposed. Later, a novel virtual machine deployment method (NVMDM) based on improved particle swarm optimization (IPSO) and Euclidean distance was put forward. It deals with problems like how to generate the initial particle swarm through the improved first-fit algorithm based on resource constraint (IFFABRC), how to define measure standard of credibility of individual and global optimal solutions of particles by combining with Bayesian transform, and how to define fitness function of particle swarm according to the multi-dimensional resource constraint relationship. The proposed NVMDM was proved superior to existing heuristic algorithm in developing performances of physical machines. It could improve utilization of CPU, memory, disk and bandwidth effectively and control task execution time of users within the range of resource constraint.

• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.865-868
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• 2001

TCM offers considerable coding gains without compromising bandwidth or signal power. But TCM decoder is more complex than convolutional Viterbi decoder. Because, the number of branches exponentially increased by the constraint length and input symbol bits. The parallelism of ACS and memory management technique of SPMM is one of the important factor for speed-up and hardware complexity. This paper proposes a multi-processing technique of ACS and also gives a memory management technique of SPMM in TCM decoders.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.1
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• pp.36-44
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• 2003

This paper proposes a Viterbi decoding scheme without trace-back operations to reduce the amount of memory storing the survivor path information, and to increase the decoding speed. The proposed decoding scheme is a modified register exchange scheme, and is verified by a simulation to give the same results as those of the conventional decoders. It is compared with the conventional decoding schemes such as the trace-back and the register exchange scheme. The memory size of the proposed scheme is reduced to 1/(5 x constraint length) of that of the register exchange scheme, and the throughput is doubled compared with that of the trace-back scheme. A decoder with a code rate of 2/3, a constraint length, K＝3 and a trace-back depth of 15 is designed using VHDL and implemented in an FPGA. It is also shown that the modified register exchange scheme can be applied to a block decoding scheme.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.285-288
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• 1998

Viterbi docoder is a maximum likelihood decoding method for convolution coding used in satellite and mobile communications. In this paper, a Viterbi decoder with constraint length of K=7, 3-soft decision and traceback depth of $\Gamma$=96 for convolution code is implemented using VHDL. The hardware size of designed decoder is reduced by 4 bit pre-traceback in the survivor memory.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.451-452
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• 2008

In this paper we describe a multi-module, multi-port memory design procedure that satisfies area and/or energy constraints. Our procedure uses ILP models to determine (a) the memory configuration with minimum area, given the energy bound, (b) the memory configuration with minimum energy, given the area bound. If we have a margin in time constraint, we break up conflict edges and expend the search space of ILP. This method effectively reduces area and power of the designed results.

• IEMEK Journal of Embedded Systems and Applications
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• v.8 no.5
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• pp.235-242
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• 2013

Recently, the number of automotive electrical and electronic system has been increased because the requirements for the convenience and safety of the drivers and passengers are raised. In most cases, the data for controlling the various sensors and automotive electrical and electronic system used in runtime should be stored on the internal or external non-volatile memory of the ECU(Electronic Control Units). However, the non-volatile memory has a constraint with write limitation due to the hardware characteristics. The limitation causes fatal accidents or unexpected results if the non-volatile memory is not managed. In this paper, we propose a management scheme for using non-volatile memory to prolong the writing times based on AUTOSAR(AUTOmotive Open System Architecture) platform. Our proposal is implemented on the CDD(Complex Device Driver) and uses an algorithm which swaps a frequently modified block for a least modified block. Through the development of the prototype, the proposed scheme extends the lifetime of non-volatile memory about 1.08 to 2.48 times than simply using the AUTOSAR standard.