• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.2
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• pp.114-121
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• 2013

As the weight of embedded memory within Systems-On-Chips(SoC) rapidly increases to 80-90% of the number of total transistors, the importance of testing embedded memory in SoC increases. This paper proposes IEEE std. 1500 wrapper based Programmable Memory Built-In Self-Test(PMBIST) architecture which can support various kinds of test algorithm. The proposed PMBIST guarantees high flexibility, programmability and fault coverage using not only March algorithms but also non-March algorithms such as Walking and Galloping. The PMBIST has an optimal hardware overhead by an optimum program instruction set and a smaller program memory. Furthermore, the proposed fault information processing scheme guarantees improvement of the memory yield by effectively supporting three types of the diagnostic methods for repair and diagnosis.

• IEIE Transactions on Smart Processing and Computing
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• v.3 no.1
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• pp.1-9
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• 2014

This paper proposes a low-latency Sample Adaptive Offset filter (SAO) architecture and its Single Instruction Multiple Data (SIMD) optimization scheme to achieve fast High Efficiency Video Coding (HEVC) decoding in a multi-core environment. According to the HEVC standard and its Test Model (HM), SAO operation is performed only at the picture level. Most realtime decoders, however, execute their sub-modules on a Coding Tree Unit (CTU) basis to reduce the latency and memory bandwidth. The proposed low-latency SAO architecture has the following advantages over picture-based SAO: 1) significantly less memory requirements, and 2) low-latency property enabling efficient pipelined multi-core decoding. In addition, SIMD optimization of SAO filtering can reduce the SAO filtering time significantly. The simulation results showed that the proposed low-latency SAO architecture with significantly less memory usage, produces a similar decoding time as a picture-based SAO in single-core decoding. Furthermore, the SIMD optimization scheme reduces the SAO filtering time by approximately 509% and increases the total decoding speed by approximately 7% compared to the existing look-up table approach of HM.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.9
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• pp.1-12
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• 1999

In this paper, we designed an embedded processor with 128Kbytes EPROM and 4Kbytes SRAM based on GMS30C2132 which RISC processor with DSP functions. And a new architecture of bus sharing to control the embedded memory and external memory unit i proposed aiming at one-cycle access between memories and CPU. For embedded 128Kbytes EPROM, we designed the new expansion interface for data size at data ordering with memory organization and the efficient interface for test. The embedded SRAM supports an extended stack area high speed DSP operation, instruction cache and variable data-length control which is accessed with 4K modulo addressing schemes. The proposed new architecture and circuits reduced the memory access cycle time from 40ns and improved operation speed 2-times for program benchmark test. The chip is occupied $108.68mm^2$ using $0.6{\mu}m$ CMOS technology.

• The KIPS Transactions:PartA
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• v.18A no.3
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• pp.109-114
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• 2011

We describe a technique for automatically proving compiler optimizations sound, meaning that their transformations are always semantics-preserving. As is well known, IR (Intermediate Representation) optimization is an important step in a compiler backend. But unfortunately, it is difficult to detect and debug the IR optimization errors for compiler developers. So, we introduce a C level error check system for detecting the correctness of these IR transformation techniques. In our system, we first create an IR-to-C converter to translate IR to C code before and after each compiler optimization phase, respectively, since our technique is based on the Memory Comparison-based Clone(MeCC) detector which is a tool of detecting semantic equivalency in C level. MeCC accepts only C codes as its input and it uses a path-sensitive semantic-based static analyzer to estimate the memory states at exit point of each procedure, and compares memory states to determine whether the procedures are equal or not. But MeCC cannot guarantee two semantic-equivalency codes always have 100% similarity or two codes with different semantics does not get the result of 100% similarity. To increase the reliability of the results, we describe a technique which comprises how to generate C codes in IR-to-C transformation phase and how to send the optimization information to MeCC to avoid the occurrence of these unexpected problems. Our methodology is illustrated by three familiar optimizations, dead code elimination, instruction scheduling and common sub-expression elimination and our experimental results show that the C level error check system is highly reliable.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.436-439
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• 2005

As mobile computers and embedded systems are becoming popular recently, we need to study how to utilize the resources such as power, space, CPU clocks, and memory efficiently. In traditional embedded system development, we were interested in resource usage based on hardware but, as software is becoming more important, we need to study how to analyze the resource usage based on software. In this research, we propose a new method called 'Instruction Level Resource Usage Analysis Method' and implement it as a resource usage analysis tool called 'I-Debugger'. I-Debugger is constructed on three layers: debugging layer which controls the execution of software on instruction level, statistic layer which gathers real-time data and convert to useful information, and analysis layer which generate useful information to specific applications. We have applied the debugger to some simple problem and found that our method is useful in developing resource efficient embedded systems.

• Journal of the Korean School Mathematics Society
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• v.2 no.1
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• pp.67-77
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• 1999

The purpose of this study was to design models of CAI programs for the graphing of quadratic functions. In order to achieve this aim, I researched the relationship between mathematics educations computer programing, and theoretical approaches of CAI. The CAI program, which was developed based on my research was then positively applied to the mathematics education class in a middle school. First of all, I selected two classes -An experimental class and a comparative class. The experimental class was taught using the CAI program and the comparative class was taught by conventional methods of instruction. The results of this study are as follows: 1. The class taught by using the CAI program scored higher academic achievement than the class taught by conventional methods of instruction. 2. The analysis of the two classes' academic scores shows that the instruction using CAI program is more effective than that by conventional methods in improving students' academic achievement. The followings are suggestion for developing CAI programs and students' understanding through this study. 1. Non computer specialists will require a few months to develope an effect CAI program. Thus, development of easier, more clearly defined and flexible models must be constructed. 2. Teachers should be eager to use pre-existing models to motivate their students irregardless of their own development of programs. 3. School should provide computer rooms with a perfect net work in proportion to class size. 4. CAI programs can make students understand faster and more directly than blackboard examples. However, inconsideration of mathematical characteristics, arithmetic by hand is more effective for the students' memory retention. Computers is an effective tool of instruction. But it is most effective when used in conjunction with other methods that complement its use.

• The KIPS Transactions:PartA
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• v.8A no.2
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• pp.107-116
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• 2001

A multithreaded model is a hybrid one which combines locality of execution of the von Neumann model with asynchronous data availability and implicit parallelism of the dataflow model. Much researches that have been made toward the advanced performance of multithreaded models are about the cache memory which have been proved to be efficient in the von Neumann model. To use an instruction cache or operand cache, the multithreaded models must have cache memories. If cache memories are added to the multithreaded model, they may have the disadvantage of high implementation cost in the mode. To solve these problems, we did not add cache memory but applied the method of executing the caching by using available registers of the multithreaded models. The available register-based caching method is one that use the registers which are not used on the execution of threads. It may accomplish the same effect as the cache memory. The multithreaded models can compute the number of available registers to be used during the process of the register optimization, and therefore this method can be easily applied on the models. By applying this method, we can also remove the access conflict and the bottleneck of frame memories. When we applied the proposed available register-based caching method, we found that there was an improved performance of the multithreaded model. Also, when the available-register-based caching method is compared with the cache based caching method, we found that there was the almost same execution overhead.

• Journal of the Korea Computer Industry Society
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• v.3 no.2
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• pp.149-158
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• 2002

This paper deals with design and verification of an arithmetic logic unit(ALU) to be used for development of optical computers. The ALU is based on optical switching device, $LiNbO_3$, which is easy to interface with electronic technology and most common in the market. It consists of an arithmetic/logic circuit performing logic operations, memory devices storing operands and the results of operations, and supplementary circuits to select instruction codes, and operates in bit-serial manner. In addition, a simulator is developed for verification of the design, and a set of basic instructions are executed in sequence and step-by-step changes in the accumulator and the memory are examined through simulations, to show that various operations are performed correctly.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.35 no.10
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• pp.940-947
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• 2007

For the performance upgrade of a supersonic jet fighter, the processor and FLCC(Flight Control Computer) Architecture were upgraded from a baseline FLCC. Prior to the hardware implementation phase, the exact CPU throughput estimation is necessary. For this purpose, an experimental method for new FLCC throughput estimation was introduced in this study.　While baseline FLCC operating, the CPU address bus was collected with logic analyzer, and then decoded to get the exact access times to each memory-memory and the number of program Instruction branches. Based on these data, a throughput test in CPU demo-board of the new FLCC configuration was performed. From test results, the CPU-Memory architecture was design-changed before FLCC hardware implementation phase. To check the flight stability degradation due to power-interrupt problem due to CPU-Memory architecture change, the piloted HILS (Hardware-In-the Loop Simulator) test was conducted.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.133-136
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• 2002

This paper presents a new method of Huffman decoding which gives a significant improvement of processing efficiency based on the reconstruction of an efficient one-dimensional array data structure incorporating the numeric interpretation of the accrued codewords in the binary tree. In the Proposed search method, the branching address is directly obtained by the arithematic operation with the incoming digit value eliminating the compare instruction needed in the binary tree search. The proposed search method gives 30% of improved Processing efficiency and the memory space of the reconstructed Huffman table is reduced to one third compared to the ordinary ‘compare and jump’ based binary tree. The experimental result with the six MPEG-2 AAC test files also shows about 198% of performance improvement compared to those of the widely used conventional sequential search method.