• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.1225-1228
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• 2005

This paper compares the differences between Java virtual machine and x86 processor in data transfer viewpoint. Memory models of JVM and x86 are analyzed and the data transfer paths are identified. As all operations must be performed to the values on operand stack, a great many data transfer operation is unavoidable in JVM. We also lists the number of data transfer operations necessary for executing some typical high-level language statements including assignment, arithmetic, conditional, and iterative statements.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.254.2-254.2
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• 2014

The Transmission Fourier Transform Infrared spectroscopy (FTIR) of SiOx charge storage layer with the richest silicon content showed an assignment at peaks around 2000~2300 cm-1. It indicated that the existence of many silicon phases and defect sources in the matrix of the SiOx films. The total hysteresis width is the sum of the flat band voltage shift (${\Delta}VFB$) due to electron and hole charging. At the range voltage sweep of ${\pm}15V$, the ${\Delta}VFB$ values increase of 0.57 V, 1.71 V, and 13.56 V with 1/2, 2/1, and 6/1 samples, respectively. When we increase the gas ratio of SiH4/N2O, a lot of defects appeared in charge storage layer, more electrons and holes are charged and the memory window also increases. The best retention are obtained at sample with the ratio SiH4/N2O=6/1 with 82.31% (3.49V) after 103s and 70.75% after 10 years. The high charge storage in 6/1 device could arise from the large amount of silicon phases and defect sources in the storage material with SiOx material. Therefore, in the programming/erasing (P/E) process, the Si-rich SiOx charge-trapping layer with SiH4/N2O gas flow ratio=6/1 easily grasps electrons and holds them, and hence, increases the P/E speed and the memory window. This is very useful for a trapping layer, especially in the low-voltage operation of non-volatile memory devices.

• KIPS Transactions on Computer and Communication Systems
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• v.2 no.2
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• pp.59-66
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• 2013

In this paper, we proposed an optimal ILP algorithm on memory address code generation for DSP in embedded system. This paper using 0-1 ILP formulations DSP address generation units should minimize the memory variable data layout. We identify the possibility of the memory assignment of variable based on the constraints condition, and register the address code which a variable instructs in the program pointer. If the process sequence of the program is declared to the program pointer, then we apply the auto-in/decrement mode about the address code of the relevant variable. And we minimize the loads on the address registers to optimize the data layout of the variable. In this paper, in order to prove the effectiveness of the proposed algorithm, FICO Xpress-MP Modeling Tools were applied to the benchmark. The result that we apply a benchmark, an optimal memory layout of the proposed algorithm then the general declarative order memory on the address/modify register to reduce the number of loads, and reduced access to the address code. Therefor, we proved to reduce the execution time of programs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.5
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• pp.369-378
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• 2003

This paper presents design and VLSI implementations of a reassembly processor for ATM/AAL. The assembly processor is responsible for processing ATM cells from the receive physical interface. It controls the transfer of the AAL payload to host memory and performs all necessary SAR and CPCS checks. We propose the improved structure of cell identification algorithm and smart scatter method for host memory management. The proposed cell identification algorithm quickly locates the appropriate reassembly VC table based on the received VPI./VCI channel value in the ATM header. The cell identification algorithm also allow complete freedom in assignment of VCI/VPI values. The reassembly processor uses a smart scatter method to write cell payload data to host memory. It maintains the scatter operation and controls the incoming DMA block during scatter DMA to host memory. The proposed reassembly processor can perform reassembly checks on AAL. OAM cell. For an AAL5 connection, only CPCS checks, including the CRC32, are performed. In this paper, we proposed a practical reassembly architecture. The design of reassembly processor has become feasible using 0.6${\mu}{\textrm}{m}$ CMOS gate array technology.

• Journal of KIISE:Software and Applications
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• v.31 no.6
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• pp.840-848
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• 2004

Garbage collecting objects in Java makes memory management easier for the programmer, but it is time consuming. Stack allocation may be an alternative which identifies stack-allocatable objects before the execution, without performance degradation. We suggest an escaping analysis recording the interprocedural movement of the method, to detect an object the method of whose creation may have been already deactivated during the access. Our approach is different from prior works, enables us to handle some cases that are missed in the previous variable - oriented approach.

• Journal of the Korean Institute of Telematics and Electronics
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• v.15 no.4
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• pp.7-13
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• 1978

This paper is concerned with the realization of sequential machines using shift-register modules as their memory elements. Other methods were to select shift-registers under the specific conditions and didn't consider the complexity of combinational circuits driving them. By using an integer valued function, all shift-registers with minimum length could be selected and an optimum assignment with lowest complexity could be obtained by comparing the number of input lines of combinational logic circuits driving them.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.4
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• pp.27-36
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• 1993

This paper proposes a shortest path allocation algorithm over the processors on the hypercube system based on the message passing techniques with the optimized module allocation. On multiprocessor systems, how to divide one task into multiple tasks efficiently is an important issue due to the hardness of the life cycle estimation of each process. To solve the life cycle discrepancies, the appropriate task assignment to each processor and the flexible communications among the processors are indispensible. With the concurrent program execution on hypercube systems, each process communicaties to others with the method of message passing. And, each processor has its own memory. The proposed algorithm generates a callable tree out of the module, assigns the weight factors, constructs the allocation graph, finds the shortest path allocation tree, and maps them with hypercube.

• International Journal of Computer Science & Network Security
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• v.21 no.2
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• pp.88-92
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• 2021

A method and a mathematical algorithm for finding a quasi-optimal assignment plan with rectangular efficiency matrices are proposed. The developed algorithm can significantly reduce the time and computer memory consumption for its implementation in comparison with optimal methods.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.2
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• pp.85-94
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• 2005

It has been reported and verified in many design experiences that a judicious utilization of the page and burst access modes supported by DRAMs contributes a great reduction in not only the DRAM access latency but also DRAM's energy consumption. Recently, researchers showed that a careful arrangement of data variables in memory directly leads to a maximum utilization of the page and burst access modes for the variable accesses, but unfortunately, found that the problems are not tractable, consequently, resorting to simple (e.g., greedy) heuristic solutions to the problems. In this parer, to improve the quality of existing solutions, we propose 0-1 ILP-based techniques which produce optimal or near-optimal solution depending on the formulation parameters. It is shown that the proposed techniques use on average 32.2%, l5.1% and 3.5% more page accesses, and 84.0%, 113.5% and 10.1% more burst accesses compared to OFU (the order of first use) and the technique in [l, 2] and the technique in [3], respectively.

• Journal of Computing Science and Engineering
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• v.5 no.2
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• pp.121-130
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• 2011

Recent research indicates that transient errors will increasingly become a critical concern in microprocessor design. As embedded processors are widely used in reliability-critical or noisy environments, it is necessary to develop cost-effective fault-tolerant techniques to protect processors against transient errors. The register file is one of the critical components that can significantly affect microprocessor system reliability, since registers are typically accessed very frequently, and transient errors in registers can be easily propagated to functional units or the memory system, leading to silent data error (SDC) or system crash. This paper focuses on investigating the impact of register file soft errors on system reliability and developing cost-effective techniques to improve the register file immunity to soft errors. This paper proposes the register vulnerability factor (RVF) concept to characterize the probability that register transient errors can escape the register file and thus potentially affect system reliability. We propose an approach to compute the RVF based on register access patterns. In this paper, we also propose two compiler-directed techniques and a hybrid approach to improve register file reliability cost-effectively by lowering the RVF value. Our experiments indicate that on average, RVF can be reduced to 9.1% and 9.5% by the hyperblock-based instruction re-scheduling and the reliability-oriented register assignment respectively, which can potentially lower the reliability cost significantly, without sacrificing the register value integrity.