• The Korean Journal of Applied Statistics
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• v.25 no.3
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• pp.403-413
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• 2012

The modifications suggested in Uhm et al. (2011) are studied using a partly parametric version of Aalen's additive risk model. A follow-up time period is partitioned into intervals, and hazard functions are estimated as a piecewise constant in each interval. A maximum likelihood estimator by iteratively reweighted least squares and variance estimates are suggested based on the model as well as evaluated by simulations using mean square error and a coverage probability, respectively. In conclusion the modifications are needed when there are a small number of uncensored deaths in an interval to estimate the piecewise constant hazard function.

• Journal of Institute of Control, Robotics and Systems
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• v.21 no.7
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• pp.669-676
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• 2015

In this paper, we described the simulation results of the phase offset performance of a clock in holdover mode which was normally operated in GPS Disciplined Oscillator (GPSDO). In the TIE model, we included the time error term caused by environmental temperature variation because one of the most important parameters of clock phase error is the frequency offset and drift caused by the variation of temperature. For the simulation, we employed Maximum Time Interval Error (MTIE) for the performance evaluation when the frequency offset and drift are estimated by using an Unbiased Finite Impulse Response (UFIR) filter with ladder algorithm. We assumed that the noise in the GPS measurement is white Gaussian with zero mean and 1 ns standard deviation, and temperature linearly varies with a slope of $1{^{\circ}C}$ per hour. From the simulation results, the followings were observed. First, with the estimation error of temperature of less than 3 % and the temperature compensation period of less than 900 seconds, the requirement of CDMA2000 phase synchronization under 10 us could be achieved for more than 40,000 seconds holdover time if we employ an OCXO (Oven Controlled Crystal Oscillator) clock. Second, in order to achieve the requirement of LTE-TDD under 1.5 us for more than 10,000 seconds holdover time, below 3 % estimation error and 500 seconds should be retained if a Rubidium clock is adopted.

• Proceedings of the KIEE Conference
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• 2008.10b
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• pp.125-126
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• 2008

A differential capacitance deviation-to-time converter for interfacing position sensor is presented. It consists of triaxial position sensor, six comparators, six current mirrors, and control logic. The prototype differential capacitance deviation-to-time interval converter has been simulated using Chartered $0.35-{\mu}m$ CMOS parameters. The simulation results show that the maximum conversion time of the converter is $350{\mu}s$ and the linearity error is less than ${\pm}0.00l5%$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.5
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• pp.893-898
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• 2017

A TDC(Time-to-Digital Converter) of counter-type is designed by $0.18{\mu}mCMOS$process and the supply voltage is 1.5 volts. The converted error of maximum $T_{CK}$ is occurred by the time difference between the start signal and the clock when the period of clock is $T_{CK}$ in the conventional TDC. And the converted error of -$T_{CK}$ is occurred by the time difference between the stop signal and the clock. However in order to compensate the disadvantage of the conventional TDC the clock is generated within the TDC circuit and the clock is synchronized with the start and stop signals. In the designed TDC circuit the conversion error is not occurred by the difference between the start signal and the click and the magnitude of conversion error is reduced (1/2)$T_{CK}$ by the time difference between the stop signal and the clock.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.5
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• pp.591-596
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• 1986

A binary continuous phase frequency shift keying (CPFSK), whose phase is a continuous function of time and instantaneous frequency is constant, is a bandwidth efficient constant envelope signalling scheme. A transmitting signal is formed by combined coding of a convolutional encoder and a binary CPFSK modulator. The signal is transmitted throuth additive white Gaussian noise(AWGN) channel. If the received signal is detected by a coherent maximum likelihood(ML) receiver, error probability can be expressed approximately in terms of minimum Euclidean distance. We propose rate 2/4 codes for the improvement of error performance without increating the data rate per bandwidth and the receiver complexity. Its minimum Euclidean distances are compared with those of rate \ulcornercodes as a function of modulation index and observation interval.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.11A
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• pp.882-890
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• 2009

In this paper, we describe a compensation method that can be used for the situation where Loran receivers lose their phase lock to the received Loran signals when Loran signals are employed for the synchronization of national infrastructures such as telecommunication networks, electric power distribution and so on. In losing the phase lock to the received signals in a Loran receiver, the inner oscillator of the receiver starts free-running and the performance of the timing synchronization signals which are locked to the oscillator's phase is very severly degraded, so the timing accuracy under 1 us for a Primary Reference Clock (PRC) required in the International Telecommunications Union (ITU) G.811 standard can not be satisfied in the situation. Therefore, in this paper, we propose a method which can compensate the phase jump by using a compensation algorithm when a Loran receiver loses its phase lock and the performance evaluation of the proposed algorithm is achieved by the Maximum Time Interval Error (MTIE) of the measured data. From the performance evaluation results, it is observed that the requirement under 1 us for a PRC can be easily achieved by using the proposed algorithm showing about 0.6 us with under 30 minutes mean interval of smoothing with 1 hour period when the loss of phase lock occurs.

• Journal of Korea Society of Digital Industry and Information Management
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• v.7 no.4
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• pp.7-14
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• 2011

Infinite failure NHPP models presented in the literature exhibit either constant, monotonic increasing or monotonic decreasing failure occurrence rate per fault (hazard function). This infinite non-homogeneous Poisson process is model which reflects the possibility of introducing new faults when correcting or modifying the software. In this paper, polynomial hazard function have been proposed, which can efficiency application for software reliability. Algorithm for estimating the parameters used to maximum likelihood estimator and bisection method. Model selection based on mean square error and the coefficient of determination for the sake of efficient model were employed. In numerical example, log power time model of the existing model in this area and the polynomial hazard function model were compared using failure interval time. Because polynomial hazard function model is more efficient in terms of reliability, polynomial hazard function model as an alternative to the existing model also were able to confirm that can use in this area.

• Journal of Broadcast Engineering
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• v.15 no.6
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• pp.803-814
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• 2010

In this paper, we propose a frame structure for modified ATSC transmission systems which is used for a terrestrial 3D HDTV broadcasting. The modified ATSC transmission systems [2] see the potential of increasing a transmission capacity at reasonable TOV (Threshold of Visibility) by modifying channel codes of conventional ATSC systems and varying modulations. We use PN symbols (Pseudorandom Noise) in a guard interval which is used for avoiding the ISI (Inter Symbol Interference) to estimate and compensate the time-varying multi path channel effectively with a maximum transmission payload. With PN symbols in the guard interval, a CIR (Channel Impulse Response) in a time domain can be estimated and a compensation in a frequency domain can be achieved for the accurate channel estimation and compensation. The prosed frame structure is applied to the modified ATSC systems and computer simulations are performed for SER (Symbol Error Rate) performances in TU (Typical Urban)-6 Channel.

• Journal of the Computational Structural Engineering Institute of Korea
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• v.36 no.2
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• pp.121-130
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• 2023

Finite element analysis is widely used to predict the structural stability and tooth contact performance of gears. This study focused on the effect of finite element modeling conditions of a spur gear on the simulation result and the model simplification. The gear body and teeth, teeth width, configuration of mesh, frictional coefficient, and simulation time interval (gear mesh cycle division) were selected for model simplification for gear analysis. The static transmission error during a single-gear mesh cycle was calculated to represent the performance of the gear, and the elapsed time was measured as a simplification factor. Contact stress distribution was also checked. The differences in maximum transmission error and elapsed time depending on the model simplification methods were analyzed. After all simplification methods were estimated, an optimal combination of the methods was defined, and the result was compared with that of the most detailed modeling methods.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.55 no.4
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• pp.224-230
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• 2006

The conventional way to implement a bidirectional converter with boost/buck has been to use two general purpose PWM ICs with a single supply voltage. In this case, when one direction mode is in operation, the other is disabled and the output of the error amplifier of the disabled IC may be saturated to a maximum value or zero. Therefore, during mode transition, a circuit which can disable the switching operation for a certain time interval is required making it impossible to get a seamless transition. In this paper, the limitations of the conventional 42V/14V bi-directional DC/DC converter implemented with general current mode PWM ICs with a single supply voltage are reviewed and a new current mode PWM controller circuit with a dual voltage system is proposed. The validity of the proposed circuit is investigated through simulation. and experiments.