• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.2
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• pp.55-60
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• 2011

Most of neural network chips use an analog-type maximum selector circuit (MS). As the increase of integration level, the analog MS has difficulties in achieving sufficient resolution. Contrary, the digital-type MS is easy to get high resolution but slower than its analog counterparts. A new high-speed digital MS circuit called MSIT (Maximum Selector with Internal Trigger-signal) is presented in this paper. The MSIT has been designed to achieves both the high reliability by using trigger-signals and high speed by removing the unnecessary waiting times. The response time of MSIT is 3.4ns for 32 data with 10-bit resolution in the simulation with 1.2V, $0.13{\mu}m$-process model parameters, which is much faster than its analog counterparts. It shows that digital MS circuits like MSIT can achieve higher speed as well as higher resolution than analog MS circuits.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.177-183
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• 2015

A high speed VLSI digital Winner-Take-All (WTA) circuit called simultaneous digital WTA (SDWTA) circuit is presented in this paper. A minimized comparison-cell (w-cell) is developed to reduce the size and to achieve high-speed. The w-cell which is suitable for VLSI implementation consists of only four transistors. With a minimized comparison-cell structure SDWTA can compare thousands of data simultaneously. SDWTA is scalable with O(mlog n) time-complexity for n of m-bit data. According to simulations, it takes 16.5 ns with $1.2V-0.13{\mu}m$ process technology in finding a winner among 1024 of 16-bit data.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.10
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• pp.1109-1116
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• 1992

Mathematical morphology, theoretical foundation for morphological filter, is very efficient for the analysis of the geometrical characteristics of signals and systems and is used as a predominant tool for smoothing the data with noise. In this study, H/W design of morphological filter is implemented to process the gray scale dilation and the erosion in the same circuit and to choose the maximum and minimum value by a selector, resulting in their education of the complexity of the circuit and an architecture for parallel processing. The structure of morphological filter consists of the structuring-element block, the image data block, the control block, the ADD block, the MIN/MAX block, etc, and is designed on an one-chip for real time operation.