• 한국통신학회:학술대회논문집
• /
• 한국통신학회 1984년도 춘계학술발표회논문집
• /
• pp.22-24
• /
• 1984

In this paper, the (15,7) cylic codesused EG(2,2) were decoded by one step majority logic decoding. This decoding algorithm is based on the properties of finite geometries and can be simply implemented for moderate length n. especially one step majority logic decoding is attractive because the complexity and the cost of the majority logic decoder increase very rapidly with L, the number of decoding steps. The theorectical and experimental results show that the majority logic decoding presented in this paper is a relatively effective decoding scheme.

• Journal of Communications and Networks
• /
• 제17권4호
• /
• pp.339-345
• /
• 2015

In this paper, we present an iterative reliability-based modified majority-logic decoding algorithm for two classes of structured low-density parity-check codes. Different from the conventional modified one-step majority-logic decoding algorithms, we design a turbo-like iterative strategy to recover the performance degradation caused by the simply flipping operation. The main computational loads of the presented algorithm include only binary logic and integer operations, resulting in low decoding complexity. Furthermore, by introducing the iterative set, a very small proportion (less than 6%) of variable nodes are involved in the reliability updating process, which can further reduce the computational complexity. Simulation results show that, combined with the factor correction technique and a well-designed non-uniform quantization scheme, the presented algorithm can achieve a significant performance improvement and a fast decoding speed, even with very small quantization levels (3-4 bits resolution). The presented algorithm provides a candidate for trade-offs between performance and complexity.

• Journal of Communications and Networks
• /
• 제17권3호
• /
• pp.213-220
• /
• 2015

In this paper, we present a reliability-based iterative proportionality-logic decoding algorithm for two classes of structured low-density parity-check (LDPC) codes. The main contributions of this paper include: 1) Syndrome messages instead of extrinsic messages are processed and exchanged between variable nodes and check nodes, which can reduce the decoding complexity; 2) a more flexible decision mechanism is developed in which the decision threshold can be self-adjusted during the iterative process. Such decision mechanism is particularly effective for decoding the majority-logic decodable codes; 3) only part of the variable nodes satisfying the pre-designed criterion are involved for the presented algorithm, which is in the proportionality-logic sense and can further reduce the computational complexity. Simulation results show that, when combined with factor correction techniques and appropriate proportionality parameter, the presented algorithm performs well and can achieve fast decoding convergence rate while maintaining relative low decoding complexity, especially for small quantized levels (3-4 bits). The presented algorithm provides a candidate for those application scenarios where the memory load and the energy consumption are extremely constrained.

• 한국정보통신학회:학술대회논문집
• /
• 한국해양정보통신학회 2010년도 추계학술대회
• /
• pp.162-164
• /
• 2010

TETRA (Terrestrial trunked radio) 표준은 제어정보의 오류정정을 위해 RM (Reed-Muller) 부호를 채택하고 있다. 본 논문에서는 BP (belief propagation), MJ (majority logic decoding) 등과 같이 잘 알려진 복호 알고리즘들을 적용하였을 경우 기대되는 비트 및 블록 오류율을 평가하고 복호 복잡도를 분석하고자 한다.

• 한국통신학회논문지
• /
• 제10권3호
• /
• pp.115-122
• /
• 1985

本 論文에서는 (7, 4) 循環코드와 (3, 1) 循環 코드의 곱의 디코더가, 같은 코드를 使用하는 보통의 다른 두 段階 多數決 理論 디코더에 비해서, 적은 수의 多數決 게이트들을 使用하도록 設計되었고, 多數決 게이트로서 ROM(read only memory)을 使用한 結果로 디코더는 간단한 構造로 製作되었다. 한 개의 受信語(혹은 21bits)을 完全히 安定시키는데 42개의 클럭 펄스가 經過하였다. 그래서 이 디코딩은 두 개의 디코더들과 二次元 語의 配列을 함께 使用한 從來의 디코딩에 비해서 디코딩 時間이 약 0.7배가 되었다.

• 한국통신학회:학술대회논문집
• /
• 한국통신학회 1985년도 춘계학술발표회논문집
• /
• pp.6-8
• /
• 1985

• 한국통신학회:학술대회논문집
• /
• 한국통신학회 1984년도 추계학술발표회논문집
• /
• pp.15-18
• /
• 1984

The majority - logic decoding algorithm for Geometry code is more simply imlemented than the known decoding algorithm for BCH codes. Thus, the moderate code word, Geometry codes provide rather effective error control. The purpose of this paper is to investigate the Reed - Muller code and to design the encoder and decoder circuit and to find the performance for (15, 11) Reed - muller code. Experimental results show that the system has not only single error - correcting ability but also good performance.

• 한국통신학회논문지
• /
• 제10권5호
• /
• pp.209-217
• /
• 1985

본 논문은 리드-뮬러 코드의 인코더 및 디코더의 설계에 관하여 체계화 시켰으며, 이러한 코드는 [J/2]개 이하의 에러를 정정할 수 있다. 리드-뮬러 코드의 해석을 이용하여, (15, 11) 리드-뮬러 코드에 대하여 순환 성질을 이용하여 인코더를 설계하고, 다수 논리 결정자 방법에 의해 디코더를 설계하였다. 또, 이러한 코드에 대해 Weight 분포 및 Performance를 구하였다. 마이크로 컴퓨터의 CPU와 Memory를 이용하기 위해 8255를 이용한 인터페이스 회로와 인코더 및 디코더를 설계, 제작하여 직접 인터페이스 시켜 실험을 하였다. 실험한 결과 한개의 에러를 완벽히 정정하였고, 한개의 정보를 수행하는데 소요되는 시간은 약 70u sec임을 알 수 있었다. 특히 (15, 11), (15, 5) 리드-뮬러 코드는 채널 에러가 $10^{-6}$~$10^{-4}$ 인 곳에 적합함을 보였다.