• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1984.04a
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• pp.22-24
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• 1984

In this paper, the (15,7) cylic codesused EG(2,2) were decoded by one step majority logic decoding. This decoding algorithm is based on the properties of finite geometries and can be simply implemented for moderate length n. especially one step majority logic decoding is attractive because the complexity and the cost of the majority logic decoder increase very rapidly with L, the number of decoding steps. The theorectical and experimental results show that the majority logic decoding presented in this paper is a relatively effective decoding scheme.

• Journal of Communications and Networks
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• v.17 no.4
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• pp.339-345
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• 2015

In this paper, we present an iterative reliability-based modified majority-logic decoding algorithm for two classes of structured low-density parity-check codes. Different from the conventional modified one-step majority-logic decoding algorithms, we design a turbo-like iterative strategy to recover the performance degradation caused by the simply flipping operation. The main computational loads of the presented algorithm include only binary logic and integer operations, resulting in low decoding complexity. Furthermore, by introducing the iterative set, a very small proportion (less than 6%) of variable nodes are involved in the reliability updating process, which can further reduce the computational complexity. Simulation results show that, combined with the factor correction technique and a well-designed non-uniform quantization scheme, the presented algorithm can achieve a significant performance improvement and a fast decoding speed, even with very small quantization levels (3-4 bits resolution). The presented algorithm provides a candidate for trade-offs between performance and complexity.

• Journal of Communications and Networks
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• v.17 no.3
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• pp.213-220
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• 2015

In this paper, we present a reliability-based iterative proportionality-logic decoding algorithm for two classes of structured low-density parity-check (LDPC) codes. The main contributions of this paper include: 1) Syndrome messages instead of extrinsic messages are processed and exchanged between variable nodes and check nodes, which can reduce the decoding complexity; 2) a more flexible decision mechanism is developed in which the decision threshold can be self-adjusted during the iterative process. Such decision mechanism is particularly effective for decoding the majority-logic decodable codes; 3) only part of the variable nodes satisfying the pre-designed criterion are involved for the presented algorithm, which is in the proportionality-logic sense and can further reduce the computational complexity. Simulation results show that, when combined with factor correction techniques and appropriate proportionality parameter, the presented algorithm performs well and can achieve fast decoding convergence rate while maintaining relative low decoding complexity, especially for small quantized levels (3-4 bits). The presented algorithm provides a candidate for those application scenarios where the memory load and the energy consumption are extremely constrained.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.10a
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• pp.162-164
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• 2010

Terrestrial trunked radio (TETRA) standard specifies shortened Reed-Muller (RM) codes as forward error correction means for control signals. In this paper, we compare decoding algorithms for RM codes in TETRA, in terms of performance and complexity trade-off. Belief propagation and majority logic decoding algorithms are selected for comparison.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.10 no.3
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• pp.115-122
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• 1985

In this paper, A decoder for the product of the (7, 4) cyclic code and the (3, 1) cyclic code was designed with less majority gates than other ordinary two-step majority-logic decoder using the same codes, then it was constucted in simple sturucture as a result of the use of a ROM as a mojority gate. It took 42 clock pulses to correct a received word(or 21bits) entirely. And so the decoding time in this decoding was multiplied by a factor of about 0.7 relative to the decoding time in the previous decoding in which two decoders and two-demensional word arrays were used together.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1985.04a
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• pp.6-8
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• 1985

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1984.10a
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• pp.15-18
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• 1984

The majority - logic decoding algorithm for Geometry code is more simply imlemented than the known decoding algorithm for BCH codes. Thus, the moderate code word, Geometry codes provide rather effective error control. The purpose of this paper is to investigate the Reed - Muller code and to design the encoder and decoder circuit and to find the performance for (15, 11) Reed - muller code. Experimental results show that the system has not only single error - correcting ability but also good performance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.10 no.5
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• pp.209-217
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• 1985

Using the Reed-Muller Codes, the encoder and decoder system has been designed and tested in this paper. The error correcting capability of this code is [J/2} or less and the error correcting procedure can be implemented easily by using simple logic circuitry. The encoding and decoding circuits are obtained by the cyclic property and for the O15, 11) Reed-Muller code majority-logic decoding is taken. The performance is measured in error probability and weight destribution. The encoder and decoder system has been designed, implemented and interfaced with the microcomputer by using the 8255 chip. Experimental results show that the system has single error-correcting capability and total execution time for a data is about 70usec. When the probability of channel error is $10^{-6}$~$10^{-4}$ the system using the (15, 11) Reed-Muller code works very good.