• Title/Summary/Keyword: macroblock

Search Result 220, Processing Time 0.018 seconds

Efficient Motion Information Representation in Splitting Region of HEVC (HEVC의 분할 영역에서 효율적인 움직임 정보 표현)

  • Lee, Dong-Shik;Kim, Young-Mo
    • Journal of Korea Multimedia Society
    • /
    • v.15 no.4
    • /
    • pp.485-491
    • /
    • 2012
  • This paper proposes 'Coding Unit Tree' based on quadtree efficiently with motion vector to represent splitting information of a Coding Unit (CU) in HEVC. The new international video coding, High Efficiency Video Coding (HEVC), adopts various techniques and new unit concept: CU, Prediction Unit (PU), and Transform Unit (TU). The basic coding unit, CU is larger than macroblock of H.264/AVC and it splits to process image-based quadtree with a hierarchical structure. However, in case that there are complex motions in CU, the more signaling bits with motion information need to be transmitted. This structure provides a flexibility and a base for a optimization, but there are overhead about splitting information. This paper analyzes those signals and proposes a new algorithm which removes those redundancy. The proposed algorithm utilizes a type code, a dominant value, and residue values at a node in quadtree to remove the addition bits. Type code represents a structure of an image tree and the two values represent a node value. The results show that the proposed algorithm gains 13.6% bit-rate reduction over the HM-1.0.

Effective hardware design for DCT-based Intra prediction encoder (DCT 기반 인트라 예측 인코더를 위한 효율적인 하드웨어 설계)

  • Cha, Ki-Jong;Ryoo, Kwang-Ki
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.16 no.4
    • /
    • pp.765-770
    • /
    • 2012
  • In this paper, we proposed an effective hardware structure using DCT-based inra-prediction mode selection to reduce computational complexity caused by intra mode decision. In this hardware structure, the input block is transformed at first and then analyzed to determine its texture directional tendency. the complexity has solved by performing intra prediction in only predicted edge direction. $4{\times}4$ DCT is calculated in one cycle using Multitransform_PE and Inta_pred_PE calculates one prediction mode in two cycles. Experimental results show that the proposed Intra prediction encoding needs only 517 cycles for one macroblock encoding. This architecture improves the performance by about 17% than previous designs. For hardware implementation, the proposed intra prediction encoder is implemented using Verilog HDL and synthesized with Megnachip $0.18{\mu}m$ standard cell library. The synthesis results show that the proposed architecture can run at 125MHz.

Area Efficient Hardware Design for Performance Improvement of SAO (SAO의 성능개선을 위한 저면적 하드웨어 설계)

  • Choi, Jisoo;Ryoo, Kwangki
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.17 no.2
    • /
    • pp.391-396
    • /
    • 2013
  • In this paper, for HEVC decoding, an SAO hardware design with less processing time and reduced area is proposed. The proposed SAO hardware architecture introduces the design processing $8{\times}8$ CU to reduce the hardware area and uses internal registers to support $64{\times}64$ CU processing. Instead of previous top-down block partitioning, it uses bottom-up block partitioning to minimize the amount of calculation and processing time. As a result of synthesizing the proposed architecture with TSMC $0.18{\mu}m$ library, the gate area is 30.7k and the maximum frequency is 250MHz. The proposed SAO hardware architecture can process the decode of a macroblock in 64 cycles.

Efficient video coding method of adaptive allocated codeword for macroblock type (마크로 블록타입에 대한 코드워드 할당이 적응적으로 가능한 효율적인 동영상 부호화 방법)

  • Park, Sea-Nae;Sim, Dong-Gyu;Lee, Ha-Hyun;Lim, Sung-Chang;Jeong, Se-Yoon;Choi, Jin-Soo
    • Proceedings of the Korean Society of Broadcast Engineers Conference
    • /
    • 2009.11a
    • /
    • pp.291-294
    • /
    • 2009
  • 최근 멀티미디어 기능을 가지는 다양한 기기가 보급되고, 이러한 기기들을 위해 다양한 화질과 해상도를 가지는 멀티미디어 서비스가 소비되고 있다. 이러한 서비스들은 목적 및 기기의 종류에 따라 전송환경이 다르기 때문에, 압축된 영상이 가지는 특성 또한 다르다. 일반적인 동영상 압축 표준에서 구문요소들에 코드워드를 할당하는 방법은 표준화 과정에서 얻어진 확률과 통계적인 수치에 의해 최적으로 결정된 것이다. 하지만 확률과 통계적인 수치는 영상의 특성에 따라 차이가 있기 때문에 최적의 코드워드는 항상 달라지는데, 현재 표준압축방법은 이러한 확률적인 특성이나 통계적인 수치를 반영하기 어려운 단점을 가진다. 이에 본 논문에서는 영상의 특징 및 부호화 조건에 따른 압축데이터의 특징을 반영하여 슬라이스 단위로 마크로 블록 타입에 대한 코드워드를 적응적으로 할당하는 방법을 제안한다. 제안하는 방법에서 부호화 조건에 따른 압축 데이터의 특징을 파악하기 위해 정해진 부호화 조건에 따라 한 번의 부호화를 수행하여 마크로 블록 타입에 대한 슬라이스 통계를 구한다. 그 다음 구해진 통계에 근거하여 마크로블록 타입에 대해 최적의 코드워드를 할당하고, 이 코드워드에 근거하여 다시 한 번 부호화를 수행하고 이렇게 발생된 비트스트림을 복호화기로 전송하게 된다. 본 논문에서 제안한 방법을 적용한 실험결과 BD-rate가 약 0.2~1.7% 정도 감소하는 결과를 얻을 수 있었다.

  • PDF

Fast Ultra-mode Selection Algorithm for H.264/AVC Video Coding with Low Complexity (저 복잡도의 H.264/AVC를 위한 고속 인트라 모드 선택 기법)

  • Kim, Jong-Ho;Jeong, Je-Chang
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.30 no.11C
    • /
    • pp.1098-1107
    • /
    • 2005
  • The emerging H.264/AVC video coding standard improves coding performance significantly by adopting many advanced techniques. This is achieved at the expense of great increasing encoder complexity. Specifically the intra prediction using RDO examines all possible combinations of coding modes, which depend on spatial directional correlation with adjacent blocks. For 4${\times}$4 luma blocks, there are 9 modes, and for 16${\times}$16 luma and 8${\times}$8 chroma blocks, there are 4 modes, respectively. Therefore the number of mode combinations for each macroblock is 592. This paper presents a method to reduce the RDO complexity using simple directional masks and neighboring modes. According to the proposed method, we reduce the number of mode combinations to 132 at the most. Experimental results show the proposed method reduces the encoding time up to $70\%$ with negligible loss of PSNR and bitrate increase compared to the H.264/AVC exhaustive search.

A Parallel Hardware Architecture for H.264/AVC Deblocking Filter (H.264/AVC를 위한 블록현상 제거필터의 병렬 하드웨어 구조)

  • Jeong, Yong-Jin;Kim, Hyun-Jip
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.43 no.10 s.352
    • /
    • pp.45-53
    • /
    • 2006
  • In this paper, we proposed a parallel hardware architecture for deblocking filter in K264/AVC. The deblocking filter has high efficiency in H.264/AVC, but it also has high computational complexity. For real time video processing, we chose a two 1-D parallel filter architecture, and tried to reduce memory access using dual-port SRAM. The proposed architecture has been described in Verilog-HDL and synthesized on Hynix 0.25um CMOS Cell Library using Synopsys Design Compiler. The hardware size was about 27.3K logic gates (without On-chip Memory) and the maximum operating frequency was 100Mhz. It consumes 258 clocks to process one macroblock, witch means it can process 47.8 HD1080P(1920pixel* 1080pixel) frames per second. It seems that it can be used for real time H.264/AVC encoding and decoding of various multimedia applications.

Effective Detection Techniques for Gradual Scene Changes on MPEG Video (MPEG 영상에서의 점진적 장면전환에 대한 효과적인 검출 기법)

  • 윤석중;지은석;김영로;고성제
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.24 no.8B
    • /
    • pp.1577-1585
    • /
    • 1999
  • In this paper, we propose detection methods for gradual scene changes such as dissolve, pan, and zoom. The proposal method to detect a dissolve region uses scene features based on spatial statistics of the image. The spatial statistics to define shot boundaries are derived from squared means within each local area. We also propose a method of the camera motion detection using four representative motion vectors in the background. Representative motion vectors are derived from macroblock motion vectors which are directly extracted from MPEG streams. To reduce the implementation time, we use DC sequences rather than fully decoded MPEG video. In addition, to detect the gradual scene change region precisely, we use all types of the MPEG frames(I, P, B frame). Simulation results show that the proposed detection methods perform better than existing methods.

  • PDF

An Efficient Hardware Design for Scaling and Transform Coefficients Decoding (스케일링과 변환계수 복호를 위한 효율적인 하드웨어 설계)

  • Jung, Hongkyun;Ryoo, Kwangki
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.16 no.10
    • /
    • pp.2253-2260
    • /
    • 2012
  • In this paper, an efficient hardware architecture is proposed for inverse transform and inverse quantization of H.264/AVC decoder. The previous inverse transform and quantization architecture has a different AC and DC coefficients decoding order. In the proposed architecture, IQ is achieved after IT regardless of the DC or AC coefficients. A common operation unit is also proposed to reduce the computational complexity of inverse quantization. Since division operation is included in the previous architecture, it will generate errors if the processing order is changed. In order to solve the problem, the division operation is achieved after IT to prevent errors in the proposed architecture. The architecture is implemented with 3-stage pipeline and a parallel vertical and horizontal IDCT is also implemented to reduce the operation cycle. As a result of analyzing the proposed ITIQ architecture operation cycle for one macroblock, the proposed one has improved by 45% than the previous one.

Duplicate Video Packet Transmission for Packet Loss-resilience (패킷 손실에 강인한 중복 비디오 패킷 전송 기법)

  • Seo Man-keon;Jeong Yo-won;Seo Kwang-deok;Kim Jae-Kyoon
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.30 no.8C
    • /
    • pp.810-823
    • /
    • 2005
  • The transmission of duplicate packets provides a great loss-resilience without undue time-delay in the video transmission over packet loss networks. But this method generally deteriorates the problem of traffic congestion because of the increased bit-rate required for duplicate transmission. In this paper, we propose an efficient packetization and duplicate transmission of video packets. The proposed method transmits only the video signal with high priority for each video macroblock that is quite small in volume but very important for the reconstruction of the video. The proposed method significantly reduces the required bit-rate for duplicate transmission. An efficient packetization method is also proposed to reduce additional packet overhead which is required for transmitting the duplicate data. The duplicated high priority data of the Previous video slice is transmitted as a Piggyback to the data Packet of the current video slice. It is shown by simulations that the proposed method remarkably improves the packet loss-resilience for video transmission only with small increase of redundant duplicated data for each slice.

An Algorithm with Low Complexity for Fast Motion Estimation in Digital Video Coding (디지털 비디오 부호화에서의 고속 움직임 추정을 위한 저복잡도 알고리즘)

  • Lee, Seung-Chul;Kim, Min-Ki;Jeong, Je-Chang
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.31 no.12C
    • /
    • pp.1232-1239
    • /
    • 2006
  • In video standards such as MPEG-1/2/4 and H.264/AVC, motion estimation / compensation(ME/MC) process causes the most encoding complexity of video encoder. The full search method, which is used in general video codecs, exhausts much encoding time because it compares current macroblock with those at all positions within search window for searching a matched block. For the alleviation of this problem, the fast search methods such as TSS, NTSS, DS and HEXBS are exploited at first. Thereafter, DS based MVFAST, PMVFAST, MAS and FAME, which utilize temporal or spacial correlation characteristics of motion vectors, are developed. But there remain the problems of image quality degradation and algorithm complexity increase. In this thesis, the proposed algorithm maximizes search speed and minimizes the degradation of image quality by determining initial search point correctly and using simple one-dimension search patterns considering motion characteristics of each frame.