• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 학술회의 논문집 정보 및 제어부문 A
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• pp.67-70
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• 2003

In this paper the main topologies of one-bit full adders, including the most interesting of those recently proposed, are analyzed and compared for speed, power consumption, and power-delay product. The comparison has been performed on circuits, optimized transistor dimension to minimize power-delay product. The investigation has been carried out with properly defined simulation runs on a Cadence environment using a 0.25-${\mu}m$ process, also including the parasitics derived from layout. Performance has been also compared for different supply voltage values. Thus design guidelines have been derived to select the most suitable topology for the design features required. This paper also proposes a novel figure of merit to realistically compare n-bit adders implemented as a chain of one-bit full adders. The results differ from those previously published both for the more realistic simulations carried out and the more appropriate figure of merit used. They show that, except for short chains of blocks or for cases where minimum power consumption is desired, topologies with only pass transistors or transmission gates are not attractive.

• Journal of Power Electronics
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• 제14권2호
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• pp.302-314
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• 2014

Due to advancements in power electronics and inverter topologies, the current controlled multilevel voltage-source pulse width modulated (PWM) inverter is usually preferred for accurate control, quick response and high dynamic performance. A multilevel topology approach is found to be best suited for overcoming many problems arising from the use of high power converters. This paper presents a comprehensive review and comparative study of several current control (CC) techniques for multilevel inverters with a special emphasis on various approaches of the hysteresis current controller. Since the hysteresis CC technique poses a problem of variable switching frequency, a ramp-comparator controller and a predictive controller to attain constant switching frequency are described along with its quantitative comparison. Furthermore, various methods have been reviewed to achieve hysteresis current control PWM with constant switching frequency operation. This paper complies various guidelines to choose a particular method suitable for application at a given power level, switching frequency and dynamic response.

• 한국전산유체공학회:학술대회논문집
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• 한국전산유체공학회 2001년도 춘계 학술대회논문집
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• pp.161-169
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• 2001

At the end of 1999, the TeraCluster Project in the KISTI Supercomputing Center was initiated to explore the possibility of PC clusters as a scientific computing platform to replace the Cray T3E system in KISTI by 2002. Since actual performance of a computing system varies significantly for different architectures, representative in-house codes from major application fields were executed to evaluate the actual performance of systems with different combination of CPU, network and network topology. As an example of practical CFD(Computational Fluid Dynamics) simulations, the flow past the Onera-M6 wing and the flow past a infinite wing were simulated on a clusters of Linux and several other hardware environments.

• 한국전산유체공학회:학술대회논문집
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• 한국전산유체공학회 2001년도 춘계 학술대회논문집
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• pp.149-154
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• 2001

Parallel performance of a Myrinet based PC-cluster was tested and compared with a conventional Fast-Ethernet system. A preconditioned Navier-Stokes code was parallelized with domain decomposition technique, and used for the parallel performance test. Speed-up ratio was examined as a major performance parameter depending on the number of processor and the network topology. As was expected, Myrinet system shows a superior parallel performance to the Fast-Ethernet system even with a single network adpater for a dual processor SMP machine. A test for the dependency on problem size also shows that network communication speed is a crucial factor for parallelized computational fluid dynamics analysis and the Myrinet system is a plausible candidate for high performance parallel computing system.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2007년도 춘계학술대회A
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• pp.608-613
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• 2007

Fine pitch microprobe arrays are microneedle-like probes for inspecting the pixel of LCD panel. They are usually made of multilayers of metallic, nonmetallic, or combination of the two. In this study, the microprobe arrays were fabricated using the process applied for MEMS fabrication technology and they consist of BeCu, BeNi, or Si. Their contacting probing force and deflection were measured using the laser equipment. The design requirement are 5gf of a minimum contact force and $150{\mu}m$ of a maximum deflection. A lot of microprobe shape are possible satisfying the requirement. A double cantilever-type microprobe having needles on both ends were applied for this study. Several candidate were chosen using the topology and shape optimization technique subjected to the design requirements. Finite element results and experimental results were compared and both gave good correlation.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2004년도 전력전자학술대회 논문집(2)
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• pp.696-699
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• 2004

This paper proposes the Low Cost Class-E Converter with Power Conversion Operation of Piezoelectric Transformer. The Power Piezoelectric transformer capacity used in the proposed circuit is 15W and the electric equivalent circuit is presented. Class E type converter has some merits such as small component count, small size, and low cost. The topology has also ZVS conditions for main switch, thus in efficiency aspect, it is also competitive for commercial feasibility. The analysis and design guideline are suggested and also they are verified by experimental results.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2012년도 추계학술대회 논문집
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• pp.63-64
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• 2012

In this paper, design relatively lightweight dual inverter SAW welding power system, compared to former large and weight system. In addition, we propose welding system topology with pulse frequency, width and current management through applying inverter to ouput.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 학술대회 논문집 전문대학교육위원
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• pp.70-74
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• 2003

The buck-boost converter is employed as the variable output PFC power stage. From the loss analysis, this topology has a high efficiency from light load to heavy load. A modified input current sensing scheme is presented to overcome the problem of the insufficient phase margin for the PFC circuit near the maximum output voltage. The variable output PFC circuit has a good performance in the wide output voltage range, under both the Boost mode when the output voltage is high and the Buck+Boost mode when the output voltage is low.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.539-540
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• 2008

This paper presents an ultra-wideband (UWB) CMOS low noise amplifier (LNA) topology that operates in 3.1-10.6GHz band. The common gate structure provides wideband input matching and flattens the passband gain. The proposed UWB amplifier is implemented in 0.18 um CMOS technology for lower band operation mode. Simulation shows a minimum NF of 2.35 dB, a power gain of $18.3{\sim}20\;dB$, better than -10 dB of input and output matching, while consuming 16.4 mW.

• 한국전산유체공학회지
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• 제2권2호
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• pp.97-103
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• 1997

A modified Delaunay triangulation technique is tested for complicated computational domain. While a simple geometry. both in topology and geometry, has been well discretized into triangular elements, a complex geometry having difficulty in triangulation had to be divided into small sub-domains of simpler shape. The present study presents a modified Delaunay triangulation method based on the data structure of geometric modeller. This approach greatly enhances the reliability of triangulation, especially in complicated computational domain. We have shown that efficiency of Delaunay triangulation can be much improved by using both the GUI (Graphic User Interface) and OOP (Object-Oriented Programming).