• Journal of KIISE:Databases
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• v.29 no.1
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• pp.58-71
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• 2002

Generally, multi-dimensional data such as image and spatial data require large amount of storage space. There is a limit to store and manage those large amount of data in single workstation. If we manage the data on parallel computing environment which is being actively researched these days, we can get highly improved performance. In this paper, we propose a parallel high-dimensional index structure that exploits the parallelism of the parallel computing environment. The proposed index structure is nP(processor)-n$\times$mD(disk) architecture which is the hybrid type of nP-nD and lP-nD. Its node structure increases fan-out and reduces the height of a index tree. Also, A range search algorithm that maximizes I/O parallelism is devised, and it is applied to K-nearest neighbor queries. Through various experiments, it is shown that the proposed method outperforms other parallel index structures.

• Proceedings of the Korea Information Processing Society Conference
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• 2017.04a
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• pp.83-86
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• 2017

단일 코어 프로세스의 성능 향상은 전력 소모, 발열 등의 이유로 한계에 달했다. 이에 대한 대안으로 멀티 코어가 등장했으며 매니 코어 기술에 대한 연구가 활발히 진행 중에 있다. 이렇듯 멀티 코어 환경이 보편화됨에 따라 병렬 프로그래밍의 중요성이 더욱 커졌다. 한편, 순수 함수형 언어 Haskell은 부수효과가 없고 다양한 병렬화 도구를 지원함으로써 다가오는 병렬 프로그래밍 시대에 적합한 언어라 할 수 있다. 이때 Haskell 병렬 프로그램의 성능은 메모리 재사용(Garbage Collection) 시간에 큰 영향을 받는다. 그래서 Haskell 병렬 프로그램의 성능 향상, 분석을 위한 메모리 프로파일링 도구가 필요하다. 이미 Haskell이 제공하는 메모리 프로파일링 도구로 ghc-gc-tune이 있지만 실행 속도 측면에서 개선이 필요하다. 본 연구에서는 분할 정복법을 이용해서 매 단계마다 탐색 영역을 4분의 1로 줄이도록 ghc-gc-tune을 개선했다. 개선된 ghc-gc-tune을 극대 독립 집합 프로그램과 K-means 프로그램에 적용한 결과, 평균 98%의 정확도로 실행 시간을 평균 7.78배 단축했다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.9
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• pp.1538-1544
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• 2006

This paper proposes a non-systolic parallel $AB^2+C$ Computing unit based on irreducible AOP order m of $GF(2^m)$. Proposed circuit have only AND gates and EX-OR gates, composes of cyclic shift operation, multiplication operation power operation power-sum operation and addition operation using a merry irreducible AOP. Suggested operating a method have an advantage high speed data processing, low power and integration because of only needs AND gates and EX-OR gates. $AB^2+C$ computing unit has delay-time of $T_A+(1+[log^m_2])T_X$.

• Proceedings of the Korea Water Resources Association Conference
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• 2008.05a
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• pp.2281-2285
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• 2008

본 연구는 인접한 저수지 간의 연계운영을 통해 용수공급효과를 제고시키기 위한 저수용량 공유기법 개발의 일환으로서 안동댐과 임하댐의 병렬저수지 시스템을 연구대상유역으로 선정하였다. 홍수기 임하댐에서 안동댐으로 전환할 수 있는 유량은 재현기간 T=50년일 때 $106.657{\times}10^6m^3$, T=80년일 때 $69.587{\times}10^6m^3$, T=100년일 때 $50.858{\times}10^6m^3$ 및 T=150년일 때 $14.771{\times}10^6m^3$로 분석되었으며, 그때의 유입용량은 각각 $344.056{\times}10^6m^3$, $376.144{\times}10^6m^3$, $391.214{\times}10^6m^3$ 및 $422.029{\times}10^6m^3$으로 나타났다. 홍수기에 안동댐에 저류된 임하댐의 이와 같은 빈도별 유입량은 갈수기에 다시 안동댐에서 임하댐으로 전환시켜 원활한 용수공급이 이루어질 수 것으로 판단된다.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.30 no.6
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• pp.21-30
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• 2002

A preconditioned Navier-Stokes code was parallelized by the domain decomposition technique, and the accuracy of the parallelized code was verified through a comparison with the result of a sequential code and experimental data. Parallel performance of the code was examined on a Myrinet based PC-cluster and a Fast-Ethernet system. Speed-up ratio was examined as a major performance parameter depending on the number of processor and the network communication topology. In this test, Myrinet system shows a superior parallel performance to the Fast-Ethernet system as was expected. A test for the dependency on problem size also shows that network communication speed in a crucial factor for parallel performance, and the Myrinet based PC-cluster is a plausible candidate for high performance parallel computing system.

• Proceedings of the Korean Information Science Society Conference
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• 2003.04a
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• pp.275-277
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• 2003

본 논문에서는 GF(2$^{m}$ )상에서 비트 직렬 Linear Feedback Shift Register (LFSR) 구조와 비트 병렬 셀룰라 오토마타(Cellular Automata, CA)구조를 혼합한 새로운 하이브리드(Hybrid) 형식의 A$B^2$곱셈기를 제안한다. 본 논문에서 제안한 곱셈기는 제곱연산을 위해 구조적으로 가장 간단한 비트 직렬 구조를 이용하고, 곱셈연산을 위해 시간 지연이 적은 비트 병렬 구조를 이용한다. 제안된 구조는 LFSR의 구조적인 특징과 Periodic Boundary CA (PBCA)의 특성, 그리고 All One Polynomial (AOP)의 특성을 조화시킴으로써 기존의 구조에 비하여 정규성을 높이고 지연 시간을 줄일 수 있는 구조이다. 제안된 곱셈기는 공개키 암호화의 핵심이 되는 지수기의 구현을 위한 효율적인 기본구조로 사용될 것으로 기대된다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.1 s.343
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• pp.45-58
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• 2006

In H/W implementation for the finite field, the use of normal basis has several advantages, especially, the optimal normal basis is the most efficient to H/W implementation in $GF(2^m)$. In this paper, we propose a new, simpler, parallel multiplier over $GF(2^m)$ having a Gaussian normal basis of type k, which performs multiplication over $GF(2^m)$ in the extension field $GF(2^{mk})$ containing a type-I optimal normal basis. For k=2,4,6 the time and area complexity of the proposed multiplier is the same as tha of the best known Reyhani-Masoleh and Hasan multiplier

• Journal of Advanced Marine Engineering and Technology
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• v.38 no.9
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• pp.1032-1038
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• 2014

In this study, an experimental study was performed to understand the boiling heat transfer characteristics of FC-72 in parallel micro-channels. The parallel micro-channels contained channels having a $0.2mm{\times}0.45mm$ [$H{\times}W$] cross section and length of 60 mm. And heat flux was varied from 16.4 to $25.6kW/m^2$ and mass fluxes from 300 to $500kg/m^2s$. The measured heat transfer coefficient was sharply decreased at lower vapor quality and then it was kept approximately constant as the vapor quality is increased. From the experimental results, the boiling heat transfer mechanism of FC-72 was confirmed and the measured heat transfer coefficient was compared and analyzed with the existing correlations to predict the heat transfer coefficient.

• Journal of the Institute of Convergence Signal Processing
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• v.11 no.3
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• pp.244-249
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• 2010

The design of error correction code with low complexity has a good attraction for next generation multi-level cell flash memory. Sharing sub-expressions is effective method to reduce complexity and chip size. This paper proposes a new design method of m-bit parallel BCH encoder based on serial linear feedback shift register structure with low complexity using sub-expression. In addition, general algorithm for obtaining the sub-expression is introduced. The sub-expression can be expressed by matrix operation between sub-matrix of generator matrix and sum of two different variables. The number of the sub-expression is restricted by. The obtained sub-expressions can be shared for implementation of different m-parallel BCH encoder. This paper is not focused on solving a problem (delay) induced by numerous fan-out, but complexity reduction, expecially the number of gates.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.2
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• pp.45-52
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• 2002

In this contributions, we propose a new MSB(most significant bit) algorithm based on AOP(All One Polynomial) and two parallel semi-systolic architectures to computes $AB^2$over finite field $GF(2^m)$. The proposed architectures are based on standard basis and use the property of irreducible AOP(All One Polynomial) which is all coefficients of 1. The proposed parallel semi-systolic architecture(PSM) has the critical path of $D_{AND2^+}D_{XOR2}$ per cell and the latency of m+1. The modified parallel semi-systolic architecture(WPSM) has the critical path of $D_{XOR2}$ per cell and has the same latency with PSM. The proposed two architectures, PSM and MPSM, have a low latency and a small hardware complexity compared to the previous architectures. They can be used as a basic architecture for exponentiation, division, and inversion. Since the proposed architectures have regularity, modularity and concurrency, they are suitable for VLSI implementation. They can be used as a basic architecture for algorithms, such as the Diffie-Hellman key exchange scheme, the Digital Signature Algorithm(DSA), and the ElGamal encryption scheme which are needed exponentiation operation. The application of the algorithms can be used cryptosystem implementation based on elliptic curve.