• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.1 s.343
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• pp.1-8
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• 2006

In this paper, we suggested a new antenna structure for the RFID(Radio Frequency IDentification) reader. The conventional RFID reader uses a loop antenna. The central area of a loop antenna shows a low magnetic field strength, especially for the case of a large loop antenna diameter. We proposed a parallel-fed multiple loop antenna. Simulation and measurement were carried out for a single loop antenna, series-fed and parallel-fed multiple loop antennas. Simulation results show that we can obtain 0.40A/m, 0.68A/m, 1.98A/m of magnetic field strengths at the central point of a reader antenna for a single loop antenna, series-fed and parallel-fed multiple loop antennas, respectively. We measured the $79mm{\time}48mm$ tag area averaged induced voltages with applying 20Vp-p same source signals to reader antennas through the resistors. Measured tag area averaged induced voltages at the central point of a reader antennas were 0.76V, 1.45V, 4.04V for a single loop antenna series-fed and parallel-fed multiple loop antennas, respectively. The results show that we can get high induced voltage which can grantee a longer reading distance with a proposed parallel-fed multiple loop antenna.

• The KIPS Transactions:PartA
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• v.11A no.2
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• pp.109-114
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• 2004

This paper presents a high-speed bit-parallel systolic divider for computing modular division A($\chi$)/B($\chi$) mod G($\chi$) in finite fields GF$(2^m)$. The presented divider is based on the binary GCD algorithm and verified through FPGA implementation. The proposed architecture produces division results at a rate of one every 1 clock cycles after an initial delay of 5m-2. Analysis shows that the proposed divider provides a significant reduction in both chip area and computational delay time compared to previously proposed systolic dividers with the same I/O format. In addition, since the proposed architecture does not restrict the choice of irreducible polynomials and has regularity and modularity, it provides a high flexibility and Scalability with respect to the field size m. Therefore, the proposed divider is well suited to VLSI implementation.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.16 no.4
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• pp.83-89
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• 2006

In H/W implementation for the finite field, the use of normal basis has several advantages, especially, the optimal normal basis is the most efficient to H/W implementation in GF($2^m$). In this paper, we propose a new, simpler, parallel multiplier over GF($2^m$) having a type II optimal normal basis, which performs multiplication over GF($2^m$) in the extension field GF($2^{2m}$). The time and area complexity of the proposed multiplier is same as the best of known type II optimal normal basis parallel multiplier.

• Proceedings of the Korea Information Processing Society Conference
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• 2017.04a
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• pp.36-39
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• 2017

길이가 같은 두 문자열의 같은 위치에 있는 문자의 순위가 모두 일치할 때, 두 문자열은 순위동형이라 한다. 순위다중패턴매칭문제는 텍스트 T와 k개의 패턴들의 집합 $P^{\prime}=\{P_1,P_2{\ldots},P_k\}$이 주어졌을 때, P'의 패턴들과 순위동형인 T의 모든 부분문자열의 위치를 찾는 문제이다. 최근 전처리단계에서 P'에 대한 이동테이블을 O(kmqlogq) 시간에 계산하여 순위다중패턴매칭문제를 해결하는 해싱기반 알고리즘이 제시되었다. 이때 P'에서 가장 짧은 패턴의 길이를 m, q-그램의 길이를 q라고 한다. 본 논문에서는 P'이 주어졌을 때, 이동테이블을 O(mqlogq) 시간에 계산하는 병렬알고리즘을 제시한다. 실험결과, 본 논문에서 제시하는 병렬알고리즘은 k개의 스레드를 이용하여 m=100, q=5에 대해 k=100일때와 k=1,000일 때 순차알고리즘보다 각각 약 12.9배, 약 215배 빠른 수행시간을 보였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.10
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• pp.1968-1976
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• 2007

This paper proposes a hybrid pseudo-noise (PN) code acquisition scheme for Multicarrier Direct Sequence - Code Division Multiple Access (MC DS-CDMA) mobile communication systems on the code acquisition performance for Nakagami-m fading channel. The hybrid acquisition scheme combines parallel search with serial search to cover the whole uncertainty region of the input code phase. It has a much simpler acquisition hardware structure than the total parallel acquisition and can achieve the mean acquisition time (MAT) slightly inferior to that of the total parallel acquisition. The closed-form expressions of the detection and false-alarm probabilities are derived.

• Proceedings of the KIPE Conference
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• 2020.08a
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• pp.79-81
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• 2020

임계모드 (Critical conduction mode, CrM) 동작을 하는 PFC 컨버터는 주파수 변동을 통한 Valley switching 동작으로 인하여 높은 효율 및 양호한 EMI 특성을 가진다. 하지만 Peak 부하가 큰 시스템에서 CrM 설계를 하게 되면 정격부하에서 비교적 높은 주파수의 동작이 불가피하여 시스템 효율이 나빠지고 높은 DC-bias 확보를 위해 인덕터 크기가 커지게 된다. 따라서 본 논문에서는 고효율 및 인덕터 사이즈 저감을 위한 임계모드에서 동작하는 두 개의 교차형 PFC 컨버터의 병렬 구동에 대해서 이야기하고자 한다.

• Journal of the Korea Society of Computer and Information
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• v.20 no.2
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• pp.1-10
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• 2015

In this paper, we propose a new multiplication algorithm for primitive polynomial with all 1 of coefficient in case that m is odd and even on finite fields $GF(3^m)$, and design the multiplier with parallel input-output module structure using the presented multiplication algorithm. The proposed multiplier is designed $(m+1)^2$ same basic cells. Since the basic cells have no a latch circuit, the multiplicative circuit is very simple and is short the delay time $T_A+T_X$ per cell unit. The proposed multiplier is easy to extend the circuit with large m having regularity and modularity by cell array, and is suitable to the implementation of VLSI circuit.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.10
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• pp.1258-1263
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• 1999

본 논문에서는 CRCW(Concurrent Read Concurrent Write)와 CREW(Concurrent Read Exclusive Write) PRAM(Parallel Random Access Machine) 모델에서 무방향성 그래프 G=(V, E)의 극대 매칭을 구하기 위해 간결한 랜덤 병렬 알고리즘을 제안한다. CRCW PRAM 모델에서 m개의 선을 가진 그래프에 대해, 제안된 매칭 알고리즘은 m개의 프로세서 상에서 {{{{ OMICRON (log m)의 기대 수행 시간을 가진다. 또한 CRCW 알고리즘을 CREW PRAM 모델에서 구현한 CREW 알고리즘은 OMICRON (log^2 m)의 기대 수행 시간을 가지지만,OMICRON (m/logm) 개의 프로세서만을 가지고 수행될 수 있다.Abstract This paper presents simple randomized parallel algorithms for finding a maximal matching in an undirected graph G=(V, E) for the CRCW and CREW PRAM models. The algorithm for the CRCW model has {{{{ OMICRON (log m) expected running time using m processors, where m is the number of edges in G We also show that the CRCW algorithm can be implemented on a CREW PRAM. The CREW algorithm runs in {{{{ OMICRON (log^2 m) expected time, but it requires only OMICRON (m / log m) processors.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.37 no.8
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• pp.1043-1050
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• 2013

Parallel robots used in industry require high stiffness or high speed because of their structural characteristics. Nowadays, the importance of rapid transportation has increased in the distribution industry. In this light, an industrial parallel robot has been developed for high-speed transfer. The developed parallel robot can handle a maximum payload of 3 kg. For a payload of 0.1 kg, the trajectory cycle time is 0.3 s (come and go), and the maximum velocity is 4.5 m/s (pick amp, place work, adept cycle). In this motion, its maximum acceleration is very high and reaches approximately 13g. In this paper, the design, analysis, and performance test results of the developed parallel robot system are introduced.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.10
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• pp.2252-2258
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• 2013

In this paper, parallel orthogonal matching pursuit (POMP) is proposed to supplement the simultaneous orthogonal matching pursuit (S-OMP) which has been widely used as a greedy algorithm for sparse signal recovery for multiple measurement vector (MMV) problem. The process of POMP is simple but effective: (1) multiple indexes maximally correlated with the observation vector are chosen at the first iteration, (2) the conventional S-OMP process is carried out in parallel for each selected index, (3) the index set which yields the minimum residual is selected for reconstructing the original sparse signal. Empirical simulations show that POMP for MMV outperforms than the conventional S-OMP both in terms of exact recovery ratio (ERR) and mean-squared error (MSE).