• Journal of Sensor Science and Technology
• /
• v.30 no.2
• /
• pp.82-87
• /
• 2021

In this paper, we propose a high-speed, low-power complementary metal-oxide semiconductor (CMOS) binary image sensor featuring a gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector based on a double-tail comparator. The GBT photodetector forms a structure in which the floating gate (n+ polysilicon) and body of the PMOSFET are tied, and amplifies the photocurrent generated by incident light. The double-tail comparator compares the output signal of a pixel against a reference voltage and returns a binary signal, and it exhibits improved power consumption and processing speed compared with those of a conventional two-stage comparator. The proposed sensor has the advantages of a high signal processing speed and low power consumption. The proposed CMOS binary image sensor was designed and fabricated using a standard 0.18 ㎛ CMOS process.

• IEIE Transactions on Smart Processing and Computing
• /
• v.3 no.2
• /
• pp.41-51
• /
• 2014

This paper describes a method to estimate the noise power using the minimum statistics approach, which was originally proposed for audio processing. The proposed minimum statistics-based method separates a noisy image into multiple frequency bands using the three-level discrete wavelet transform. By assuming that the output of the high-pass filter contains both signal detail and noise, the proposed algorithm extracts the region of pure noise from the high frequency band using an appropriate threshold. The region of pure noise, which is free from the signal detail part and the DC component, is well suited for minimum statistics condition, where the noise power can be extracted easily. The proposed algorithm reduces the computational load significantly through the use of a simple processing architecture without iteration with an estimation accuracy greater than 90% for strong noise at 0 to 40dB SNR of the input image. Furthermore, the well restored image can be obtained using the estimated noise power information in parametric image restoration algorithms, such as the classical parametric Wiener or ForWaRD image restoration filters. The experimental results show that the proposed algorithm can estimate the noise power accurately, and is particularly suitable for fast, low-cost image restoration or enhancement applications.

• Journal of Sensor Science and Technology
• /
• v.29 no.2
• /
• pp.82-88
• /
• 2020

In this paper, we propose a complementary metal-oxide semiconductor (CMOS) binary image sensor with a gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector using a double-tail comparator for high-speed and low-power operations. The GBT photodetector is based on a PMOSFET tied with a floating gate (n+ polysilicon) and a body that amplifies the photocurrent generated by incident light. A double-tail comparator compares an input signal with a reference voltage and returns the output signal as either 0 or 1. The signal processing speed and power consumption of a double-tail comparator are superior over those of conventional comparator. Further, the use of a double-sampling circuit reduces the standard deviation of the output voltages. Therefore, the proposed CMOS binary image sensor using a double-tail comparator might have advantages, such as low power consumption and high signal processing speed. The proposed CMOS binary image sensor is designed and simulated using the standard 0.18 ㎛ CMOS process.

• Journal of Sensor Science and Technology
• /
• v.27 no.6
• /
• pp.362-367
• /
• 2018

A complementary metal oxide semiconductor (CMOS) binary image sensor is proposed for low-power and low-noise operation. The proposed binary image sensor has the advantages of reduced power consumption and fixed pattern noise (FPN). A gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector is used as the proposed CMOS binary image sensor. The GBT PMOSFET-type photodetector has a floating gate that amplifies the photocurrent generated by incident light. Therefore, the sensitivity of the GBT PMOSFET-type photodetector is higher than that of other photodetectors. The proposed CMOS binary image sensor consists of a pixel array with $394(H){\times}250(V)$ pixels, scanners, bias circuits, and column parallel readout circuits for binary image processing. The proposed CMOS binary image sensor was analyzed by simulation. Using the dynamic comparator, a power consumption reduction of approximately 99.7% was achieved, and this performance was verified by the simulation by comparing the results with those of a two-stage comparator. Also, it was confirmed using simulation that the FPN of the proposed CMOS binary image sensor was successfully reduced by use of the double sampling process.

• ETRI Journal
• /
• v.31 no.6
• /
• pp.717-724
• /
• 2009

This paper describes a 1.2 V 12 b 60 MS/s CMOS analog front-end (AFE) employing low-power and flexible design techniques for image signal processing. An op-amp preset technique and programmable capacitor array scheme are used in a variable gain amplifier to reduce the power consumption with a small area of the AFE. A pipelined analog-to-digital converter with variable resolution and a clock detector provide operation flexibility with regard to resolution and speed. The AFE is fabricated in a 0.13 ${\mu}m$ CMOS process and shows a gain error of 0.68 LSB with 0.0352 dB gain steps and a differential/integral nonlinearity of 0.64/1.58 LSB. The signal-to-noise ratio of the AFE is 59.7 dB at a 60 MHz sampling frequency. The AFE occupies 1.73 $mm^2$ and dissipates 64 mW from a 1.2 V supply. Also, the performance of the proposed AFE is demonstrated by an implementation of an image signal processing platform for digital camcorders.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.33 no.10C
• /
• pp.798-804
• /
• 2008

This paper proposes a low-power circuit for detecting and correcting L2 cache errors during microprocessor data image processing. A simplescalar-ARM is used to analyze input and output data by accessing the microprocessor's L2 cache during image processing in terms of the data input and output frequency as well as the variation of each bit for 32-bit processing. The circuit is implemented based on an H-matrix capable of achieving low power consumption by extracting bits with small and large amounts of variation and allocating bits with similarities in variation. Simulation is performed using H-spice to compare power consumption of the proposed circuit to the odd-weight-column code used in a conventional microprocessor. The experimental results indicated that the proposed circuit reduced power consumption by 17% compared to the odd-weight-column code.

• IEIE Transactions on Smart Processing and Computing
• /
• v.5 no.5
• /
• pp.310-318
• /
• 2016

Emerging technologies such as the Internet of Things (IoT) and the Advanced Driver Assistant System (ADAS) often have image transmission functions with tough constraints, like low power and/or low delay, which require that they adopt line-based, low memory compression methods instead of existing frame-based image compression standards. Bit rate control in the conventional frame-based compression systems requires a lot of hardware resources when the scope of handled data falls at the frame level. On the other hand, attempts to reduce the heavy hardware resource requirement by focusing on line-level processing yield uneven image quality through the frame. In this paper, we propose a bit rate control that maintains consistency in image quality through the frame and improves the legibility of text regions. To find the line characteristics, the proposed bit rate control tests each line for ease of compression and the existence of text. Experiments on the proposed bit rate control show peak signal-to-noise ratios (PSNRs) similar to those of conventional bit rate controls, but with the use of significantly fewer hardware resources.

• The Transactions of the Korean Institute of Electrical Engineers P
• /
• v.56 no.1
• /
• pp.19-22
• /
• 2007

We developed a low cost digital X-Ray image capturing system using a CCD camera, instead of using the high cost image plate and image intensifier. In order to reduce the system volume, we directly made the dark box shorter than the previous model. Using the graphic language, we developed a program in order for post-processing the images captured by the CCD camera. This program improves the image resolving power.

• IEMEK Journal of Embedded Systems and Applications
• /
• v.8 no.1
• /
• pp.25-29
• /
• 2013

Recently ARM processor's processing power has been increasing rapidly as it has been applied to consumer electronics products. Because of its computing power and low power consumption, it is used to various embedded systems.( including vision processing systems.) Embedded linux that provides well-made platform and GUI is also a powerful tool for ARM based embedded systems. So short period to develop is one of major advantages to the ARM based embedded system. However, for real-time date processing applications such as an image processing system, ARM needs additional equipments such as FPGA that is suitable to parallel processing applications. In this paper, we developed an embedded system using ARM processor and FPGA. FPGA takes time consuming image preprocessing and numerical algorithms needs floating point arithmetic and user interface are implemented using the ARM processor. Overall processing speed of the system is 60 frames/sec of VGA images.

• Journal of Power Electronics
• /
• v.17 no.3
• /
• pp.725-732
• /
• 2017

This paper proposed a real-time, low-cost, fast transistor open-circuit fault diagnosis method for voltage-source inverter fed induction motors. A transistor open-circuit changes the symmetry of the inverter topology, leading to different similarities among three phase load currents. In this paper, dynamic time warping is proposed to describe the similarities among load currents. The proposed diagnosis is independent of the system model and needs no extra sensors or electrical circuits. Both simulation and experimental results show the high efficiency of the proposed fault diagnosis method.